Issued Patents All Time
Showing 26–50 of 739 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12228961 | Memory system using asymmetric source-synchronous clocking | — | 2025-02-18 |
| 12223207 | Memory component having internal read-modify-write operation | Thomas Vogelsang | 2025-02-11 |
| 12222829 | Memory module with dedicated repair devices | Brent Haukness, John Eric Linstadt, Scott C. Best | 2025-02-11 |
| 12223209 | High capacity, high performance memory system | — | 2025-02-11 |
| 12216543 | Fault tolerant memory systems and components with interconnected and redundant data interfaces | Kenneth L. Wright | 2025-02-04 |
| 12213548 | Hybrid memory module | John Eric Linstadt, Kenneth L. Wright | 2025-02-04 |
| 12211540 | Protocol for refresh between a memory controller and a memory device | Brent Haukness | 2025-01-28 |
| 12198780 | Memory controllers, systems, and methods supporting multiple request modes | Richard E. Perego | 2025-01-14 |
| 12200860 | Load reduced memory module | Suresh Rajan | 2025-01-14 |
| 12197354 | Memory module threading with staggered data transfers | Hongzhong Zheng | 2025-01-14 |
| 12196805 | Methods and apparatus for testing inaccessible interface circuits in a semiconductor device | — | 2025-01-14 |
| 12197731 | Memory system with threaded transaction support | Ely Tsern | 2025-01-14 |
| 12190974 | DRAM retention test method for dynamic error correction | Ely Tsern, Suresh Rajan, Thomas Vogelsang | 2025-01-07 |
| 12190990 | Deferred fractional memory row activation | James E. Harris, Thomas Vogelsang, Ian Shaeffer | 2025-01-07 |
| 12164447 | Off-module data buffer | Christopher Haywood | 2024-12-10 |
| 12148462 | High capacity memory system using standard controller component | Suresh Rajan, Scott C. Best | 2024-11-19 |
| 12147362 | Deterministic operation of storage class memory | Brent Haukness | 2024-11-19 |
| 12135645 | Nonvolatile physical memory with DRAM cache | John Eric Linstadt, Christopher Haywood | 2024-11-05 |
| 12130757 | Memory module with reduced read/write turnaround overhead | Craig E. Hampel | 2024-10-29 |
| 12130759 | Protocol including timing calibration between memory request and data transfer | Holden D. Jessup | 2024-10-29 |
| 12130703 | Memory component with error-detect-correct code interface | Brent Haukness, Lawrence Lai | 2024-10-29 |
| 12119042 | Low-power source-synchronous signaling | Jared L. Zerbe | 2024-10-15 |
| 12119819 | Power-up switch-interconnect configuration | Robert Fu | 2024-10-15 |
| 12111723 | Memory repair method and apparatus based on error code tracking | Ely Tsern | 2024-10-08 |
| 12105975 | Adjustable access energy and access latency memory system and devices | John Eric Linstadt | 2024-10-01 |