Issued Patents All Time
Showing 51–75 of 118 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7730282 | Method and apparatus for avoiding data dependency hazards in a microprocessor pipeline architecture using a multi-bit age vector | Nathan Samuel Nunamaker, Sanjay Patel | 2010-06-01 |
| 7725625 | Latency insensitive FIFO signaling protocol | Kenneth Alan Dockser, Victor Roberts Augsburg, Jeffrey Todd Bridges, Robert Douglas Clancy, Thomas Andrew Sartorius | 2010-05-25 |
| 7721067 | Translation lookaside buffer manipulation | Brian Joseph Kopec, Victor Roberts Augsburg, Jeffrey Todd Bridges, Thomas Andrew Sartorius | 2010-05-18 |
| 7711930 | Apparatus and method for decreasing the latency between instruction cache and a pipeline processor | Richard W. Doing, Brian Michael Stempel, Steven R. Testa, Kenichi Tsuchiya | 2010-05-04 |
| 7698536 | Method and system for providing an energy efficient register file | Thomas Andrew Sartorius, Jeffrey Todd Bridges, Michael Scott McIlvaine, Gregory Christopher Burda | 2010-04-13 |
| 7685373 | Selective snooping by snoop masters to locate updated data | Bernard C. Drerup, Jaya Prakash Subramaniam Ganasan, Richard Gerard Hofmann, Thomas Andrew Sartorius, Thomas Philip Speier +1 more | 2010-03-23 |
| 7669039 | Use of register renaming system for forwarding intermediate results between constituent instructions of an expanded instruction | Michael Scott McIlvaine, Nathan Samuel Nunamaker, Thomas Andrew Sartorius, Rodney Wayne Smith | 2010-02-23 |
| 7650466 | Method and apparatus for managing cache partitioning using a dynamic boundary | Brian Michael Stempel, Jeffrey Todd Bridges, Thomas Andrew Sartorius, Rodney Wayne Smith, Robert Douglas Clancy +1 more | 2010-01-19 |
| 7624256 | System and method wherein conditional instructions unconditionally provide output | Thomas Andrew Sartorius, Jeffrey Todd Bridges, Kenneth Alan Dockser, Michael Scott McIlvaine, Rodney Wayne Smith | 2009-11-24 |
| 7624254 | Segmented pipeline flushing for mispredicted branches | Rodney Wayne Smith, Michael Scott McIlvaine, Thomas Andrew Sartorius | 2009-11-24 |
| 7617387 | Methods and system for resolving simultaneous predicted branch instructions | Rodney Wayne Smith, Brian Michael Stempel, Thomas Andrew Sartorius | 2009-11-10 |
| 7610463 | Method and apparatus for performing an atomic semaphore operation | Thomas Philip Speier, Richard Gerard Hofmann, Thomas Andrew Sartorius | 2009-10-27 |
| 7587580 | Power efficient instruction prefetch mechanism | Thomas Andrew Sartorius, Victor Roberts Augsburg, Jeffrey Todd Bridges, Michael Scott McIlvaine, Rodney Wayne Smith | 2009-09-08 |
| 7568070 | Instruction cache having fixed number of variable length instructions | Jeffrey Todd Bridges, Rodney Wayne Smith, Thomas Andrew Sartorius | 2009-07-28 |
| 7523265 | Systems and arrangements for promoting a line to exclusive in a fill buffer of a cache | Praveen Karandikar, Michael B. Mitchell, Thomas Philip Speier, Paul M. Steinmetz | 2009-04-21 |
| 7500045 | Minimizing memory barriers when enforcing strongly-ordered requests in a weakly-ordered processing system | Richard Gerard Hofmann, Thomas Andrew Sartorius, Thomas Philip Speier, Jaya Prakash Subramaniam Ganasan | 2009-03-03 |
| 7478228 | Apparatus for generating return address predictions for implicit and explicit subroutine calls | Brian Michael Stempel, Thomas Andrew Sartorius, Rodney Wayne Smith | 2009-01-13 |
| 7454538 | Latency insensitive FIFO signaling protocol | Kenneth Alan Dockser, Victor Roberts Augsburg, Jeffrey Todd Bridges, Robert Douglas Clancy, Thomas Andrew Sartorius | 2008-11-18 |
| 7437537 | Methods and apparatus for predicting unaligned memory access | Jeffrey Todd Bridges, Victor Roberts Augsburg, Thomas Andrew Sartorius | 2008-10-14 |
| 7426626 | TLB lock indicator | Victor Roberts Augsburg, Jeffrey Todd Bridges, Thomas Andrew Sartorius | 2008-09-16 |
| 7424563 | Two-level interrupt service routine | Michael Egnoah Birenbach, Gregory Brookshire, Stephen G. Geist, Richard A. Moore, Thomas Andrew Sartorius +1 more | 2008-09-09 |
| 7421529 | Method and apparatus to clear semaphore reservation for exclusive access to shared memory | Thomas Philip Speier, Thomas Andrew Sartorius, Jaya Prakash Subramaniam Ganasan | 2008-09-02 |
| 7421568 | Power saving methods and apparatus to selectively enable cache bits based on known processor state | Brian Michael Stempel, Jeffrey Todd Bridges, Rodney Wayne Smith, Thomas Andrew Sartorius | 2008-09-02 |
| 7415638 | Pre-decode error handling via branch correction | Rodney Wayne Smith, Brian Michael Stempel, Jeffrey Todd Bridges, Thomas Andrew Sartorius | 2008-08-19 |
| 7406613 | Translation lookaside buffer (TLB) suppression for intra-page program counter relative or absolute address branch instructions | Thomas Andrew Sartorius, Rodney Wayne Smith, Brian Michael Stempel | 2008-07-29 |