Issued Patents All Time
Showing 26–50 of 118 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8782356 | Auto-ordering of strongly ordered, device, and exclusive transactions across multiple memory regions | Jason Panavich, Thomas Andrew Sartorius, Thomas Philip Speier | 2014-07-15 |
| 8661229 | Power efficient instruction prefetch mechanism | Thomas Andrew Sartorius, Victor Roberts Augsburg, Jeffrey Todd Bridges, Michael Scott McIlvaine, Rodney Wayne Smith | 2014-02-25 |
| 8612690 | Method for filtering traffic to a physically-tagged data cache | Robert Douglas Clancy, Thomas Philip Speier | 2013-12-17 |
| 8527713 | Cache locking without interference from normal allocations | Victor Roberts Augsburg, Jeffrey Todd Bridges, Thomas Andrew Sartorius | 2013-09-03 |
| 8499208 | Method and apparatus for scheduling BIST routines | Anand Krishnamurthy, Clint Wayne Mumford, Jason Panavich, Ketan Vitthal Patel, Ravi Rajagopalan +1 more | 2013-07-30 |
| 8443162 | Methods and apparatus for dynamically managing banked memory | Thomas Philip Speier, Ravi Rajagopalan | 2013-05-14 |
| 8438372 | Link stack repair of erroneous speculative update | Brian Michael Stempel, Rodney Wayne Smith | 2013-05-07 |
| 8438371 | Link stack repair of erroneous speculative update | Brian Michael Stempel, Rodney Wayne Smith | 2013-05-07 |
| 8386716 | Apparatus and methods to reduce castouts in a multi-level cache hierarchy | Thomas Philip Speier, Thomas Andrew Sartorius | 2013-02-26 |
| 8352682 | Methods and apparatus for issuing memory barrier commands in a weakly ordered storage system | Thomas Philip Speier, Thomas Andrew Sartorius | 2013-01-08 |
| 8341383 | Method and a system for accelerating procedure return sequences | Michael William Morrow | 2012-12-25 |
| 8239657 | Address translation method and apparatus | Brian Joseph Kopec, Victor Roberts Augsburg, Thomas Andrew Sartorius | 2012-08-07 |
| 8127114 | System and method for executing instructions prior to an execution stage in a processor | Kiran Ravi Seth, Michael Scott McIlvaine, Nathan Samuel Nunamaker | 2012-02-28 |
| 8082428 | Methods and system for resolving simultaneous predicted branch instructions | Rodney Wayne Smith, Brian Michael Stempel, Thomas Andrew Sartorius | 2011-12-20 |
| 8078803 | Apparatus and methods to reduce castouts in a multi-level cache hierarchy | Thomas Philip Speier, Thomas Andrew Sartorius | 2011-12-13 |
| 8060701 | Apparatus and methods for low-complexity instruction prefetch system | Michael William Morrow | 2011-11-15 |
| 7984279 | System and method for using a working global history register | Brian Michael Stempel, Thomas Andrew Sartorius, Rodney Wayne Smith | 2011-07-19 |
| 7971044 | Link stack repair of erroneous speculative update | Brian Michael Stempel, Rodney Wayne Smith | 2011-06-28 |
| 7949861 | Method and apparatus for managing instruction flushing in a microprocessor's instruction pipeline | Michael Scott McIlvaine, Thomas Andrew Sartorius | 2011-05-24 |
| 7934025 | Content terminated DMA | Kevin Allen Sapp | 2011-04-26 |
| 7917702 | Data prefetch throttle | Michael William Morrow | 2011-03-29 |
| 7827392 | Sliding-window, block-based branch target address cache | Rodney Wayne Smith, Thomas Andrew Sartorius, Brian Michael Stempel | 2010-11-02 |
| 7805588 | Caching memory attribute indicators with cached memory data field | Jeffrey Todd Bridges, Thomas Andrew Sartorius, Brian Michael Stempel, Rodney Wayne Smith | 2010-09-28 |
| 7761774 | High speed CAM lookup using stored encoded key | Jeffrey Herbert Fischer, Michael ThaiThanh Phan, Chiaming Chai | 2010-07-20 |
| 7752396 | Promoting a line from shared to exclusive in a cache | Praveen Karandikar, Michael B. Mitchell, Thomas Philip Speier, Paul M. Steinmetz | 2010-07-06 |