Issued Patents All Time
Showing 101–125 of 129 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7134100 | Method and apparatus for efficient register-transfer level (RTL) power estimation | Srivaths Ravi, Anand Raghunathan | 2006-11-07 |
| 7131081 | Scalable scan-path test point insertion technique | Seongmoon Wang | 2006-10-31 |
| 7019674 | Content-based information retrieval architecture | Srihari Cadambi, Joseph Kilian, Pranav Ashar | 2006-03-28 |
| 6735744 | Power mode based macro-models for power estimation of electronic circuits | Anand Raghunathan, Ganesh Lakshminarayana, Nachiketh Rao Potlapally, Michael Hsiao | 2004-05-11 |
| 6732310 | Peripheral partitioning and tree decomposition for partial scan | Arun Balakrishnan | 2004-05-04 |
| 6505316 | Peripheral partitioning and tree decomposition for partial scan | Arun Balakrishnan | 2003-01-07 |
| 6467058 | Segmented compaction with pruning and critical fault elimination | Surendra K. Bommu, Kiran B. Doreswamy | 2002-10-15 |
| 6378096 | On-line partitioning for sequential circuit test generation | Kiran B. Doreswamy, Surendra K. Bommu, Xijiang Lin | 2002-04-23 |
| 6345373 | System and method for testing high speed VLSI devices using slower testers | Angela Krstic, Kwang-Ting Cheng | 2002-02-05 |
| 6223316 | Vector restoration using accelerated validation and refinement | Surendra K. Bommu, Kiran B. Doreswamy | 2001-04-24 |
| 6145106 | State relaxation based subsequence removal method for fast static compaction in sequential circuits | Michael Hsiao | 2000-11-07 |
| 6134687 | Peripheral partitioning and tree decomposition for partial scan | Arun Balakrishnan | 2000-10-17 |
| 6018813 | Identification and test generation for primitive faults | Kwang-Ting Cheng, Angela Krstic | 2000-01-25 |
| 5987636 | Static test sequence compaction using two-phase restoration and segment manipulation | Surendra K. Bommu, Kiran B. Doreswamy | 1999-11-16 |
| 5983381 | Partitioning and reordering methods for static test sequence compaction of sequential circuits | Michael Hsiao | 1999-11-09 |
| 5958077 | Method for testing asynchronous circuits | Savita Banerjee, Rabindra K. Roy | 1999-09-28 |
| 5875196 | Deriving signal constraints to accelerate sequential test generation | Vijay Gangaram, Steven G. Rothweiler | 1999-02-23 |
| 5731983 | Method for synthesizing a sequential circuit | Arunkumar BALAKRISHNAN | 1998-03-24 |
| 5726996 | Process for dynamic composition and test cycles reduction | Anand Raghunathan | 1998-03-10 |
| 5663888 | Redesign of sequential circuits to reduce clock period | — | 1997-09-02 |
| 5657240 | Testing and removal of redundancies in VLSI circuits with non-boolean primitives | Steven G. Rothweiler, Vishwani D. Agrawal | 1997-08-12 |
| 5574734 | Test generation of sequential circuits using software transformations | Arun Balakrishnan | 1996-11-12 |
| 5555188 | Optimal retiming of synchronous logic circuits | — | 1996-09-10 |
| 5506852 | Testing VLSI circuits for defects | Igor Rivin | 1996-04-09 |
| 5502647 | Resynthesis and retiming for optimum partial scan testing | Sujit Dey | 1996-03-26 |