Issued Patents All Time
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8214172 | Systems and methods for locating defective components of a circuit | Xiangyu Tang | 2012-07-03 |
| 7818643 | Method for blocking unknown values in output response of scan test patterns for testing circuits | Srimat Chakradhar | 2010-10-19 |
| 7730373 | Test data compression method for system-on-chip using linear-feedback shift register reseeding | Zhanglei Wang | 2010-06-01 |
| 7610540 | Method for generating, from a test cube set, a generator configured to generate a test pattern | Kedarnath Balakrishnan, Wenlong Wei, Srimat Chakradhar | 2009-10-27 |
| 7610527 | Test output compaction with improved blocking of unknown values | Kedarnath Balakrishnan, Srimat Chakradhar | 2009-10-27 |
| 7610539 | Method and apparatus for testing logic circuit designs | Kedarnath Balakrishnan, Wenlong Wei, Srimat Chakradhar | 2009-10-27 |
| 7577540 | Re-configurable embedded core test protocol for system-on-chips (SOC) and circuit boards | Srimat Chakradhar, Kedarnath Balakrishnan | 2009-08-18 |
| 7562321 | Method and apparatus for structured ASIC test point insertion | Srimat Chakradhar | 2009-07-14 |
| 7484151 | Method and apparatus for testing logic circuit designs | Kedarnath Balakrishnan, Wenlong Wei, Srimat Chakradhar | 2009-01-27 |
| 7313746 | Test output compaction for responses with unknown values | Chia-Tso Chao, Srimat Chakradhar | 2007-12-25 |
| 7313743 | Hybrid scan-based delay testing technique for compact and high fault coverage test set | Xiao Liu, Srimat Chakradhar | 2007-12-25 |
| 7302626 | Test pattern compression with pattern-independent design-independent seed compression | Kedarnath Balakrishnan, Srimat Chakradhar | 2007-11-27 |
| 7284176 | Externally-loaded weighted random test pattern compression | Srimat Chakradhar | 2007-10-16 |
| 7222277 | Test output compaction using response shaper | Srimat Chakradhar, Chia-Tso Chao | 2007-05-22 |
| 7188323 | Restricted scan reordering technique to enhance delay fault coverage | Wei Li, Srimat Chakradhar | 2007-03-06 |
| 7131081 | Scalable scan-path test point insertion technique | Srimat Chakradhar | 2006-10-31 |
| 6886124 | Low hardware overhead scan based 3-weight weighted random BIST architectures | — | 2005-04-26 |