PL

Pei-Ing Lee

NT Nanya Technology: 28 patents #23 of 775Top 3%
IBM: 12 patents #9,222 of 70,183Top 15%
SC Siemens Components: 2 patents #3 of 30Top 10%
MT Materials Technology: 1 patents #6 of 14Top 45%
SA Siemens Aktiengesellschaft: 1 patents #10,653 of 22,248Top 50%
📍 Hsinchu, VT: #1 of 2 inventorsTop 50%
Overall (All Time): #71,319 of 4,157,543Top 2%
42
Patents All Time

Issued Patents All Time

Showing 26–42 of 42 patents

Patent #TitleCo-InventorsDate
6368912 Method of fabricating an isolation structure between a vertical transistor and a deep trench capacitor Chi-Han Chang, Tzu-En He, Hsin-Chuan Tsai 2002-04-09
6211006 Method of forming a trench-type capacitor Hsin-Chuan Tsai, Yi-Nan Chen 2001-04-03
6117726 Method of making a trench capacitor Hsin-Chuan Tsai 2000-09-12
6100117 Method for manufacturing DRAM having a redundancy circuit region Chung-Peng Hao, Chung-Lin Huang, Lee Chung Yuan, Wu-Hsiung Chen 2000-08-08
5886320 Laser ablation with transmission matching for promoting energy coupling to a film stack Antonio R. Gallo 1999-03-23
5872390 Fuse window with controlled fuse oxide thickness William A. Klaasen, Alexander Mitwalsky 1999-02-16
5834829 Energy relieving crack stop Bettina Dinkel, Ernest N. Levine 1998-11-10
5798301 Method of manufacturing metal interconnect structure for an integrated circuit with improved electromigration reliability Bernd Vollmer, Darryl D. Restaino, Bill Klaasen 1998-08-25
5760475 Refractory metal-titanium nitride conductive structures John Cronin, Carter W. Kaanta, Michael A. Leach 1998-06-02
5641992 Metal interconnect structure for an integrated circuit with improved electromigration reliability Bernd Vollmer, Darryl D. Restaino, Bill Klaasen 1997-06-24
5608257 Fuse element for effective laser blow in an integrated circuit device Frank Prein 1997-03-04
5401675 Method of depositing conductors in high aspect ratio apertures using a collimator Thomas J. Licata, Thomas L. McDevitt, Paul C. Parries, Scott L. Pennington, James G. Ryan +1 more 1995-03-28
5262354 Refractory metal capped low resistivity metal conductor lines and vias William J. Cote, Thomas E. Sandwick, Bernd Vollmer, Victor Vynorius, Stuart H. Wolff 1993-11-16
5229257 Process for forming multi-level coplanar conductor/insulator films employing photosensitive polymide polymer compositions John Cronin, Carter W. Kaanta, Rosemary A. Previti-Kelly, James G. Ryan, Jung Hyuk YOON 1993-07-20
5034348 Process for forming refractory metal silicide layers of different thicknesses in an integrated circuit Thomas J. Hartswick, Carter W. Kaanta, Terrance M. Wright 1991-07-23
4962058 Process for fabricating multi-level integrated circuit wiring structure from a single metal deposit John Cronin 1990-10-09
4919750 Etching metal films with complexing chloride plasma Robert C. Bausmith, William J. Cote, John Cronin, Karey Holland, Carter W. Kaanta +1 more 1990-04-24