Issued Patents All Time
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11121081 | Antifuse element | Chung-Lin Huang | 2021-09-14 |
| 10985783 | Correction device | — | 2021-04-20 |
| 10778147 | Drive level auto-tuning system, drive level auto-tuning method and non-transitory computer readable medium | — | 2020-09-15 |
| 10769553 | Integrated circuit device and circuitry | — | 2020-09-08 |
| 10760936 | Semiconductor device and method of sensing a change in a level of a liquid therein | — | 2020-09-01 |
| 7094638 | Method of forming gate structure | Jin-Tau Huang, Yi-Nan Chen, Tse-Yao Huang | 2006-08-22 |
| 7071075 | STI forming method for improving STI step uniformity | Yi-Nan Chen | 2006-07-04 |
| 6984566 | Damascene gate process | Yi-Nan Chen | 2006-01-10 |
| 6977134 | Manufacturing method of a MOSFET gate | Hui-Min Mao, Yi-Nan Chen, Tzu-Ching Tsai | 2005-12-20 |
| 6929996 | Corner rounding process for partial vertical transistor | Yi-Nan Chen, Ming-Cheng Chang | 2005-08-16 |
| 6884714 | Method of forming shallow trench isolation with chamfered corners | Tse-Yao Huang, Yi-Nan Chen | 2005-04-26 |
| 6576530 | Method of fabricating shallow trench isolation | Yi-Nan Chen, Chung-Yuan Lee | 2003-06-10 |
| 6403483 | Shallow trench isolation having an etching stop layer and method for fabricating same | Chung-Lin Huang, Chung-Yuan Lee, Yih-Ren Shao, Pei-Ing Lee | 2002-06-11 |
| 6100117 | Method for manufacturing DRAM having a redundancy circuit region | Chung-Lin Huang, Lee Chung Yuan, Pei-Ing Lee, Wu-Hsiung Chen | 2000-08-08 |