Issued Patents All Time
Showing 151–170 of 170 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6051878 | Method of constructing stacked packages | Salman Akram | 2000-04-18 |
| 6008996 | Interdigitated leads-over-chip lead frame, device, and method for supporting an integrated circuit die | Aaron Schoenfeld | 1999-12-28 |
| 6008531 | Hybrid frame with lead-lock tape | Larry D. Kinsman, Timothy J. Allen | 1999-12-28 |
| 5994166 | Method of constructing stacked packages | Salman Akram | 1999-11-30 |
| 5977616 | Interdigitated leads-over-chip lead frame, device, and method for supporting an integrated circuit die | Aaron Schoenfeld | 1999-11-02 |
| 5973935 | Interdigitated leads-over-chip lead frame for supporting an integrated circuit die | Aaron Schoenfeld | 1999-10-26 |
| 5955777 | Lead frame assemblies with voltage reference plane and IC packages including same | David J. Corisis, Terry R. Lee | 1999-09-21 |
| 5915166 | Tape under frame for conventional-type IC package assembly | David J. Corisis, Larry D. Kinsman | 1999-06-22 |
| 5907184 | Integrated circuit package electrical enhancement | David J. Corisis | 1999-05-25 |
| 5903443 | Interdigitated leads-over-chip lead frame, device, and method for supporting an integrated circuit die | Aaron Schoenfeld | 1999-05-11 |
| 5897340 | Hybrid frame with lead-lock tape | Larry D. Kinsman, Timothy J. Allen | 1999-04-27 |
| 5872398 | Reduced stress LOC assembly including cantilevered leads | Jerrold L. King, Larry D. Kinsman, David J. Corisis | 1999-02-16 |
| 5763945 | Integrated circuit package electrical enhancement with improved lead frame design | David J. Corisis | 1998-06-09 |
| 5729049 | Tape under frame for conventional-type IC package assembly | David J. Corisis, Larry D. Kinsman | 1998-03-17 |
| 5717246 | Hybrid frame with lead-lock tape | Larry D. Kinsman, Timothy J. Allen | 1998-02-10 |
| 5677566 | Semiconductor chip package | Jerrold L. King | 1997-10-14 |
| 5616953 | Lead frame surface finish enhancement | Jerrold L. King, Syed Sajid Ahmad | 1997-04-01 |
| 5440241 | Method for testing, burning-in, and manufacturing wafer scale integrated circuits and a packaged wafer assembly produced thereby | Jerrold L. King, Warren M. Farnworth, George P. McGill | 1995-08-08 |
| 5150194 | Anti-bow zip lead frame design | Chender Huang | 1992-09-22 |
| 5140405 | Semiconductor assembly utilizing elastomeric single axis conductive interconnect | Jerrold L. King, Warren M. Farnworth, George P. McGill | 1992-08-18 |