Issued Patents All Time
Showing 151–175 of 225 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7805258 | System and method for film stress and curvature gradient mapping for screening problematic wafers | Hsueh-Hung Fu, Chih-Wei Chang, Chin-Piao Chang, Shing-Chyang Pan, Wei-Jung Lin +1 more | 2010-09-28 |
| 7741699 | Semiconductor device having ultra-shallow and highly activated source/drain extensions | Keh-Chiang Ku, Chun-Feng Nieh, Li-Ping Huang, Chih-Chiang Wang, Chien-Hao Chen +3 more | 2010-06-22 |
| 7728645 | Pulse generator | SHEN-AN CHEN, RONG-CONG HUNG, You-Ren Lin, RONG-HWANG HORNG, YAW-SHEN LAI | 2010-06-01 |
| 7727900 | Surface preparation for gate oxide formation that avoids chemical oxide formation | Matt Yeh, Shun Wu Lin, Chi-Chun Chen | 2010-06-01 |
| 7713854 | Gate dielectric layers and methods of fabricating gate dielectric layers | Chi-Chun Chen, Matt Yeh, Mong-Song Liang, Jennifer Chen, Da-Yuan Lee | 2010-05-11 |
| 7638396 | Methods for fabricating a semiconductor device | Da-Yuan Lee, Chi-Chun Chen | 2009-12-29 |
| 7592619 | Epitaxy layer and method of forming the same | Pang-Yen Tsai, Liang-Gi Yao, Chun-Chieh Lin, Wen-Chin Lee | 2009-09-22 |
| 7544561 | Electron mobility enhancement for MOS devices with nitrided polysilicon re-oxidation | Wenli Lin, Da-Yuan Lee, Chi-Chun Chen | 2009-06-09 |
| 7528028 | Super anneal for process induced strain modulation | Mong-Song Liang, Chien-Hao Chen, Chun-Feng Nieh, Pang-Yen Tsai, Tze-Liang Lee | 2009-05-05 |
| 7494857 | Advanced activation approach for MOS devices | Chien-Hao Chen, Tze-Liang Lee, Keh-Chiang Ku, Chun-Feng Nieh, Li-Ting Wang +1 more | 2009-02-24 |
| 7488419 | Water faucet containing water mixed with ozone | Hsiang-Shih Wang | 2009-02-10 |
| 7482211 | Junction leakage reduction in SiGe process by implantation | Chun-Feng Nieh, Chien-Hao Chen, Keh-Chiang Ku, Tze-Liang Lee | 2009-01-27 |
| 7410854 | Method of making FUSI gate and resulting structure | Liang-Gi Yao, Hun-Jan Tao, Mong-Song Liang | 2008-08-12 |
| 7393766 | Process for integration of a high dielectric constant gate insulator layer in a CMOS device | Ming-Fang Wang, Chien-Hao Chen, Liang-Gi Yao | 2008-07-01 |
| 7384486 | Chamber cleaning method | Ming-Ho Yang, Liang-Gei Yao | 2008-06-10 |
| 7361572 | STI liner modification method | Chien-Hao Chen, Vincent S. Chang, Chia-Lin Chen, Tze-Liang Lee | 2008-04-22 |
| 7357838 | Relaxed silicon germanium substrate with low defect density | Chun-Chieh Lin, Yee-Chia Yeo, Chien-Chao Huang, Chao-Hsiung Wang, Tien-Chih Chang +4 more | 2008-04-15 |
| 7351994 | Noble high-k device | Liang-Gi Yao, Tien-Chih Chang, Ming-Fang Wang, Mong-Song Liang | 2008-04-01 |
| 7335544 | Method of making MOSFET device with localized stressor | Chien-Hao Chen, Donald Y. Chao, Tze-Liang Lee | 2008-02-26 |
| 7316970 | Method for forming high selectivity protection layer on semiconductor device | Chien-Hao Chen, Ju-Wang Hsu, Chia-Lin Chen, Tze-Liang Lee | 2008-01-08 |
| 7303996 | High-K gate dielectric stack plasma treatment to adjust threshold voltage characteristics | Ming-Fang Wang, Tuo-Hung Hou, Kai-Lin Mai, Liang-Gi Yao | 2007-12-04 |
| 7262096 | NAND flash memory cell row and manufacturing method thereof | Cheng-Yuan Hsu, Chih-Wei Hung | 2007-08-28 |
| 7259050 | Semiconductor device and method of making the same | Chien-Hao Chen, Chia-Lin Chen, Tze-Liang Lee, Ju-Wang Hsu | 2007-08-21 |
| 7229919 | Semiconductor device having a random grained polysilicon layer and a method for its manufacture | Chia-Lin Chen, Liang-Gi Yao | 2007-06-12 |
| 7202142 | Method for producing low defect density strained -Si channel MOSFETS | Kuen-Chyr Lee, Liang-Gi Yao, Mong-Song Liang | 2007-04-10 |