Issued Patents All Time
Showing 176–200 of 281 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7288845 | Fabrication of wire bond pads over underlying active devices, passive devices and/or dielectric layers in integrated circuits | Sehat Sutardja, Albert Wu, Mou-Shiung Lin | 2007-10-30 |
| 7282804 | Structure of high performance combo chip and processing method | — | 2007-10-16 |
| 7276422 | Post passivation interconnection schemes on top of the IC chips | Mou-Shiung Lin | 2007-10-02 |
| 7271033 | Method for fabricating chip package | Mou-Shiung Lin, Ching-Cheng Huang | 2007-09-18 |
| 7265047 | Post passivation interconnection schemes on top of the IC chips | Mou-Shiung Lin | 2007-09-04 |
| 7265045 | Method for fabricating thermal compliant semiconductor chip wiring structure for chip scale packaging | Eric Lin | 2007-09-04 |
| 7208834 | Bonding structure with pillar and cap | Chien-Kang Chou, Shih-Hsiung Lin, Hsi-Shan Kuo | 2007-04-24 |
| 6936531 | Process of fabricating a chip structure | Mou-Shiung Lin, Ching-Cheng Huang | 2005-08-30 |
| 6917119 | Low fabrication cost, high performance, high reliability chip scale package | Ming-Ta Lei, Ching-Cheng Huang, Chuen-Jye Lin | 2005-07-12 |
| 6818545 | Low fabrication cost, fine pitch and high reliability solder bump | Mou-Shiung Lin, Ching-Cheng Huang | 2004-11-16 |
| 6818495 | Method for forming high purity silicon oxide field oxide isolation region | Min-Hsiung Chiang, Jenn Ming Huang | 2004-11-16 |
| 6809935 | Thermally compliant PCB substrate for the application of chip scale packages | — | 2004-10-26 |
| 6806570 | Thermal compliant semiconductor chip wiring structure for chip scale packaging | Eric Lin | 2004-10-19 |
| 6800941 | Integrated chip package structure using ceramic substrate and method of manufacturing the same | Mou-Shiung Lin, Ching-Cheng Huang | 2004-10-05 |
| 6798073 | Chip structure and process for forming the same | Mou-Shiung Lin, Ching-Cheng Huang | 2004-09-28 |
| 6784087 | Method of fabricating cylindrical bonding structure | Chien-Kang Chou, Shih-Hsiung Lin, Hsi-Shan Kuo | 2004-08-31 |
| 6762115 | Chip structure and process for forming the same | Mou-Shiung Lin, Ching-Cheng Huang | 2004-07-13 |
| 6759275 | Method for making high-performance RF integrated circuits | Mou-Shiung Lin | 2004-07-06 |
| 6756295 | Chip structure and process for forming the same | Mou-Shiung Lin, Ching-Cheng Huang | 2004-06-29 |
| 6746898 | Integrated chip package structure using silicon substrate and method of manufacturing the same | Mou-Shiung Lin, Ching-Cheng Huang | 2004-06-08 |
| 6734563 | Post passivation interconnection schemes on top of the IC chips | Mou-Shiung Lin | 2004-05-11 |
| 6700162 | Chip structure to improve resistance-capacitance delay and reduce energy loss of the chip | Mou-Shiung Lin, Ching-Cheng Huang | 2004-03-02 |
| 6673698 | Thin film semiconductor package utilizing a glass substrate with composite polymer/metal interconnect layers | Mou-Shiung Lin, Ching-Cheng Huang | 2004-01-06 |
| 6649509 | Post passivation metal scheme for high-performance integrated circuit devices | Mou-Shiung Lin, Ming-Ta Lei, Ching-Cheng Huang | 2003-11-18 |
| 6642136 | Method of making a low fabrication cost, high performance, high reliability chip scale package | Ming-Ta Lei, Ching-Cheng Huang, Chuen-Jye Lin | 2003-11-04 |