Issued Patents All Time
Showing 201–225 of 281 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6635936 | SRAM layout for relaxing mechanical stress in shallow trench isolation technology | Shou-Gwo Wuu, Dun-Nian Yaung, Jeng-Han Lee | 2003-10-21 |
| 6613606 | Structure of high performance combo chip and processing method | — | 2003-09-02 |
| 6605528 | Post passivation metal scheme for high-performance integrated circuit devices | Mou-Shiung Lin, Ming-Ta Lei, Ching-Cheng Huang | 2003-08-12 |
| 6600186 | Process technology architecture of embedded DRAM | Mong-Song Liang | 2003-07-29 |
| 6522009 | Apparatus to electroless plate a metal layer while eliminating the photo electric effect | — | 2003-02-18 |
| 6495912 | Structure of ceramic package with integrated passive devices | Ching-Cheng Huang, Mou-Shiung Lin | 2002-12-17 |
| 6495442 | Post passivation interconnection schemes on top of the IC chips | Mou-Shiung Lin | 2002-12-17 |
| 6476460 | Stacked gate MOS structure for multiple voltage power supply applications | Mong-Song Liang, Choe-San Yoo | 2002-11-05 |
| 6433665 | High efficiency thin film inductor | Kuo-Ching Huang, Tse-Liang Ying | 2002-08-13 |
| 6399997 | High performance system-on-chip using post passivation process and glass substrates | Mou-Shiung Lin | 2002-06-04 |
| 6387801 | Method and an apparatus to electroless plate a metal layer while eliminating the photoelectric effect | — | 2002-05-14 |
| 6373369 | High efficiency thin film inductor | Kuo-Ching Huang, Tse-Liang Ying | 2002-04-16 |
| 6346729 | Pseudo silicon on insulator MOSFET device | Mong-Song Liang, Chue-San Yoo | 2002-02-12 |
| 6327682 | Wafer burn-in design for DRAM and FeRAM devices | Pien Chien | 2001-12-04 |
| 6278352 | High efficiency thin film inductor | Kuo-Ching Huang, Tse-Liang Ying | 2001-08-21 |
| 6268281 | Method to form self-aligned contacts with polysilicon plugs | Cheng-Yeh Shih, Chung-Long Chang | 2001-07-31 |
| 6265301 | Method of forming metal interconnect structures and metal via structures using photolithographic and electroplating or electro-less plating procedures | Chen-Jong Wang | 2001-07-24 |
| 6239458 | Polysilicon-via structure for four transistor, triple polysilicon layer SRAM cell including two polysilicon layer load resistor | Jhon Jhy Liaw | 2001-05-29 |
| 6214698 | Shallow trench isolation methods employing gap filling doped silicon oxide dielectric layer | Jhon Jhy Liaw, Kuei-Ying Lee, Chu-Yun Fu, Kong-Beng Thei | 2001-04-10 |
| 6180530 | Self-aligned contact structure | Jhon Jhy Liaw | 2001-01-30 |
| 6174754 | Methods for formation of silicon-on-insulator (SOI) and source/drain-on-insulator(SDOI) transistors | Mong-Song Liang, Boon-Khim Liew | 2001-01-16 |
| 6172411 | Self-aligned contact structures using high selectivity etching | Li-Chih Chao, Jhon Jhy Liaw, Yuan-Chang Huang | 2001-01-09 |
| 6136633 | Trench-free buried contact for locos isolation | Dun-Nian Yaung, Shou-Gwo Wuu | 2000-10-24 |
| 6136638 | Process technology architecture of embedded DRAM | Mong-Song Liang | 2000-10-24 |
| 6117722 | SRAM layout for relaxing mechanical stress in shallow trench isolation technology and method of manufacture thereof | Shou-Gwo Wuu, Dun-Nian Yaung, Jeng-Han Lee | 2000-09-12 |