Issued Patents All Time
Showing 226–250 of 281 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6093616 | Method of manufacture of stacked gate MOS structure for multiple voltage power supply applications | Mong-Song Liang, Chue-San Yoo | 2000-07-25 |
| 6090674 | Method of forming a hole in the sub quarter micron range | Hung-Chang Hsieh, Hua-Tai Lin, Jhon Jhy Liaw | 2000-07-18 |
| 6071773 | Process for fabricating a DRAM metal capacitor structure for use in an integrated circuit | Mong-Song Liang | 2000-06-06 |
| 6071783 | Pseudo silicon on insulator MOSFET device | Mong-Song Liang, Chue-San Yoo | 2000-06-06 |
| 6071798 | Method for fabricating buried contacts | Dun-Nian Yaung, Shou-Gwo Wuu, Jhon Jhy Liaw | 2000-06-06 |
| 6037199 | SOI device for DRAM cells beyond gigabit generation and method for making the same | Jenn Ming Huang | 2000-03-14 |
| 5998249 | Static random access memory design and fabrication process featuring dual self-aligned contact structures | Jhon Jhy Liaw | 1999-12-07 |
| 5965927 | Integrated circuit having an opening for a fuse | Chue-San Yoo, Hsien-Wei Chin | 1999-10-12 |
| 5960276 | Using an extra boron implant to improve the NMOS reverse narrow width effect in shallow trench isolation process | Jhon Jhy Liaw, Dun-Nian Yaung | 1999-09-28 |
| 5955768 | Integrated self-aligned butt contact process flow and structure for six transistor full complementary metal oxide semiconductor static random access memory cell | Jhon Jhy Liaw | 1999-09-21 |
| 5926697 | Method of forming a moisture guard ring for integrated circuit applications | Dun-Nian Yaung, Shou-Gwo Wuu, Hsien-Wei Chin | 1999-07-20 |
| 5926706 | Method for making a trench-free buried contact with low resistance on semiconductor integrated circuits | Jhon Jhy Liaw | 1999-07-20 |
| 5915192 | Method for forming shallow trench isolation | Jhon Jhy Liaw | 1999-06-22 |
| 5905289 | Planarized metallurgy structure for a semiconductor and process of fabrication | — | 1999-05-18 |
| 5900658 | Logic and single level polysilicon DRAM devices fabricated on the same semiconductor chip | Chue-San Yoo, Mong-Song Liang | 1999-05-04 |
| 5879966 | Method of making an integrated circuit having an opening for a fuse | Chue-San Yoo, Hsien-Wei Chin | 1999-03-09 |
| 5872063 | Self-aligned contact structures using high selectivity etching | Li-Chih Chao, Jhon Jhy Liaw, Yuan-Chang Huang | 1999-02-16 |
| 5866451 | Method of making a semiconductor device having 4t sram and mixed-mode capacitor in logic | Chue-San Yoo, Mong-Song Liang | 1999-02-02 |
| 5866449 | Method of making polysilicon-via structure for four transistor, triple polysilicon layer SRAM cell including two polysilicon layer load resistor | Jhon Jhy Liaw | 1999-02-02 |
| 5861673 | Method for forming vias in multi-level integrated circuits, for use with multi-level metallizations | Chue-San Yoo | 1999-01-19 |
| 5851912 | Modified tungsten-plug contact process | Jhon Jhy Liaw, Ming-Chang Teng | 1998-12-22 |
| 5843817 | Process for integrating stacked capacitor DRAM devices with MOSFET devices used for high performance logic circuits | Mong-Song Liang | 1998-12-01 |
| 5843816 | Integrated self-aligned butt contact process flow and structure for six transistor full complementary metal oxide semiconductor static random access memory cell | Jhon Jhy Liaw | 1998-12-01 |
| 5827764 | Method for reducing the contact resistance of a butt contact | Jhon Jhy Liaw | 1998-10-27 |
| 5801415 | Non-volatile-memory cell for electrically programmable read only memory having a trench-like coupling capacitors | Mong-Song Liang | 1998-09-01 |