Issued Patents All Time
Showing 251–275 of 281 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5792684 | Process for fabricating MOS memory devices, with a self-aligned contact structure, and MOS logic devices with salicide, both on a single semiconductor chip | Mong-Song Liang | 1998-08-11 |
| 5789313 | Process for producing a semiconductor device with a planar top surface | — | 1998-08-04 |
| 5780331 | Method of making buried contact structure for a MOSFET device in an SRAM cell | Jhon Jhy Liaw | 1998-07-14 |
| 5757060 | Contamination guard ring for semiconductor integrated circuit applications | John Wei, Ying-Chen Chao | 1998-05-26 |
| 5752771 | Integrated circuit module fixing mechanism for temperature cycling test | King-Ho Ping | 1998-05-19 |
| 5751044 | Manufacture device of four transistor sram cell layout and device | — | 1998-05-12 |
| 5747381 | Technique for the removal of residual spin-on-glass (SOG) after full SOG etchback | Lin-June Wu, Chen-Hua Yu | 1998-05-05 |
| 5729041 | Protective film for fuse window passivation for semiconductor integrated circuit applications | Chue-San Yoo | 1998-03-17 |
| 5726497 | Upward plug filled via hole device | Ying-Chen Chao, Ting-Hwang Lin | 1998-03-10 |
| 5726932 | Trench free SRAM cell structure | Jenn Ming Huang, Ming-Chih Chung | 1998-03-10 |
| 5721146 | Method of forming buried contact architecture within a trench | Jhon Jhy Liaw, Hung-Chi Hsiao | 1998-02-24 |
| 5719079 | Method of making a semiconductor device having high density 4T SRAM in logic with salicide process | Chue-San Yoo, Mong-Song Liang | 1998-02-17 |
| 5712201 | Fabrication method for integrating logic and single level polysilicon DRAM devices on the same semiconductor chip | Chue-San Yoo, Mong-Song Liang | 1998-01-27 |
| 5707897 | Non-volatile-memory cell for electrically programmable read only memory having a trench-like coupling capacitors | Mong-Song Liang | 1998-01-13 |
| 5686336 | Method of manufacture of four transistor SRAM cell layout | — | 1997-11-11 |
| 5674770 | Method of fabricating an SRAM device with a self-aligned thin film transistor structure | Shou-Gwo Wuu | 1997-10-07 |
| 5672538 | Modified locus isolation process in which surface topology of the locos oxide is smoothed | Jhon Jhy Liaw, Sou-Wein Kuo | 1997-09-30 |
| 5672896 | Three stage ESD protection device | Mong-Song Liang | 1997-09-30 |
| 5665657 | Spin-on-glass partial etchback planarization process | — | 1997-09-09 |
| 5654231 | Method of eliminating buried contact trench in SRAM technology | Mong-Song Liang, Chun-Yi Shih | 1997-08-05 |
| 5614430 | Anti-punchthrough ion implantation for sub-half micron channel length MOSFET devices | Mong-Song Liang | 1997-03-25 |
| 5610081 | Integrated circuit module fixing method for temperature cycling test | King-Ho Ping | 1997-03-11 |
| 5605853 | Method of making a semiconductor device having 4 transistor SRAM and floating gate memory cells | Chue-San Yoo, Mong-Song Liang | 1997-02-25 |
| 5593911 | Method of making ESD protection circuit with three stages | Mong-Song Liang | 1997-01-14 |
| 5591664 | Method of increasing the capacitance area in DRAM stacked capacitors using a simplified process | Chen-Jong Wang | 1997-01-07 |