Issued Patents All Time
Showing 126–150 of 281 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7932603 | Chip structure and process for forming the same | Mou-Shiung Lin, Ching-Cheng Huang | 2011-04-26 |
| 7923366 | Post passivation interconnection schemes on top of IC chip | Mou-Shiung Lin | 2011-04-12 |
| 7919865 | Post passivation interconnection schemes on top of IC chip | Mou-Shiung Lin | 2011-04-05 |
| 7919867 | Chip structure and process for forming the same | Mou-Shiung Lin, Ching-Cheng Huang | 2011-04-05 |
| 7919873 | Structure of high performance combo chip and processing method | Mou-Shiung Lin | 2011-04-05 |
| 7915734 | Chip structure and process for forming the same | Mou-Shiung Lin, Ching-Cheng Huang | 2011-03-29 |
| 7915161 | Post passivation interconnection schemes on top of IC chip | Mou-Shiung Lin | 2011-03-29 |
| 7915157 | Chip structure and process for forming the same | Mou-Shiung Lin, Ching-Cheng Huang | 2011-03-29 |
| 7906849 | Chip structure and process for forming the same | Mou-Shiung Lin, Ching-Cheng Huang | 2011-03-15 |
| 7906422 | Chip structure and process for forming the same | Mou-Shiung Lin, Ching-Cheng Huang | 2011-03-15 |
| 7902067 | Post passivation interconnection schemes on top of the IC chips | Mou-Shiung Lin | 2011-03-08 |
| 7898058 | Integrated chip package structure using organic substrate and method of manufacturing the same | Mou-Shiung Lin, Ching-Cheng Huang | 2011-03-01 |
| 7892965 | Post passivation interconnection schemes on top of IC chip | Mou-Shiung Lin | 2011-02-22 |
| 7863739 | Low fabrication cost, fine pitch and high reliability solder bump | Mou-Shiung Lin, Ching-Cheng Huang | 2011-01-04 |
| 7534718 | Post passivation interconnection schemes on top of IC chips | Mou-Shiung Lin | 2009-05-19 |
| 7524759 | Post passivation interconnection schemes on top of IC chip | Mou-Shiung Lin | 2009-04-28 |
| 7521812 | Method of wire bonding over active area of a semiconductor circuit | Ying-Chih Chen, Mou-Shiung Lin | 2009-04-21 |
| 7517778 | Structure of high performance combo chip and processing method | Mou-Shiung Lin | 2009-04-14 |
| 7511376 | Circuitry component with metal layer over die and extending to place not over die | Mou-Shiung Lin, Ching-Cheng Huang | 2009-03-31 |
| 7498196 | Structure and manufacturing method of chip scale package | Ching-Cheng Huang, Mou-Shiung Lin | 2009-03-03 |
| 7482259 | Chip structure and process for forming the same | Mou-Shiung Lin, Ching-Cheng Huang | 2009-01-27 |
| 7479450 | Post passivation interconnection schemes on top of the IC chips | Mou-Shiung Lin | 2009-01-20 |
| 7470988 | Chip structure and process for forming the same | Mou-Shiung Lin, Ching-Cheng Huang | 2008-12-30 |
| 7470927 | Semiconductor chip with coil element over passivation layer | Wen-Chieh Lee, Mou-Shiung Lin, Chien-Kang Chou, Yi-Cheng Liu, Chiu-Ming Chou | 2008-12-30 |
| 7468316 | Low fabrication cost, fine pitch and high reliability solder bump | Mou-Shiung Lin, Ching-Cheng Huang | 2008-12-23 |