Issued Patents All Time
Showing 151–175 of 400 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11770936 | Stack of planar capacitors including capacitors with non-linear polar material and linear dielectric for common mode compensation in a memory bit-cell | Rajeev Kumar Dokania, Noriyuki Sato, Tanay Gosavi, Amrita Mathuriya | 2023-09-26 |
| 11769790 | Rapid thermal annealing (RTA) methodologies for integration of perovskite-material based trench capacitors | Niloy Mukherjee, Somilkumar J. Rathi, Jason Y. Wu, Pratyush Pandey, Zeying Ren +8 more | 2023-09-26 |
| 11769543 | Writing scheme for 1TNC ferroelectric memory bit-cell with plate-lines parallel to a bit-line and with individual switches and control on the plate-lines of the bit-cell | Rajeev Kumar Dokania, Amrita Mathuriya | 2023-09-26 |
| 11765908 | Memory device fabrication through wafer bonding | Mauricio Manfrini, Noriyuki Sato, James David Clarkson, Abel Fernandez, Somilkumar J. Rathi +4 more | 2023-09-19 |
| 11764790 | Majority logic gate having paraelectric input capacitors coupled to a conditioning scheme | Rajeev Kumar Dokania, Amrita Mathuriya, Rafael Rios, Ikenna Odinaka, Robert Menezes +1 more | 2023-09-19 |
| 11764190 | 3D stacked compute and memory with copper pillars | Rajeev Kumar Dokania, Amrita Mathuriya, Ramamoorthy Ramesh | 2023-09-19 |
| 11765909 | Process integration flow for embedded memory enabled by decoupling processing of a memory area from a non-memory area | Noriyuki Sato, Tanay Gosavi, Niloy Mukherjee, Rajeev Kumar Dokania, Amrita Mathuriya | 2023-09-19 |
| 11758738 | Integration of ferroelectric memory devices with transistors | Rajeev Kumar Dokania, Ramamoorthy Ramesh, Gaurav Thareja, Amrita Mathuriya | 2023-09-12 |
| 11758708 | Stack of non-planar capacitors including capacitors with non-linear polar material and linear dielectric for common mode compensation in a memory bit-cell | Rajeev Kumar Dokania, Noriyuki Sato, Tanay Gosavi, Amrita Mathuriya | 2023-09-12 |
| 11757452 | OR-and-invert logic based on a mix of majority or minority logic gate with non-linear input capacitors and other logic gates | Amrita Mathuriya, Rafael Rios, Ikenna Odinaka, Darshak Doshi, Rajeev Kumar Dokania | 2023-09-12 |
| 11757043 | Doped polar layers and semiconductor device incorporating same | Ramesh Ramamoorthy, Gaurav Thareja | 2023-09-12 |
| 11751404 | FinFET transistor based resistive random access memory | Abhishek A. Sharma, Gregory K. Chen, Phil Knag, Ram Krishnamurthy, Raghavan Kumar +3 more | 2023-09-05 |
| 11751403 | Common mode compensation for 2T1C non-linear polar material based memory bit-cell | Rajeev Kumar Dokania, Noriyuki Sato, Tanay Gosavi, Amrita Mathuriya | 2023-09-05 |
| 11750197 | AND-OR-invert logic based on a mix of majority OR minority logic gate with non-linear input capacitors and other logic gates | Amrita Mathuriya, Rafael Rios, Ikenna Odinaka, Darshak Doshi, Rajeev Kumar Dokania | 2023-09-05 |
| 11748537 | Computer-aided design tool for logic synthesis of a mix of CMOS gates and majority and minority logic circuits | Ikenna Odinaka, Darshak Doshi, Rajeev Kumar Dokania, Amrita Mathuriya | 2023-09-05 |
| 11744081 | Ferroelectric device film stacks with texturing layer which is part of a bottom electrode, and method of forming such | Niloy Mukherjee, Ramamoorthy Ramesh, James David Clarkson, FNU Atiquzzaman, Gabriel Antonio Paulius Velarde +1 more | 2023-08-29 |
| 11742860 | Fabrication of a majority logic gate having non-linear input capacitors | Rafael Rios, Neal Reynolds, Ikenna Odinaka, Robert Menezes, Rajeev Kumar Dokania +2 more | 2023-08-29 |
| 11741428 | Iterative monetization of process development of non-linear polar material and devices | Niloy Mukherjee, Noriyuki Sato, Tanay Gosavi, Somilkumar J. Rathi, James David Clarkson +3 more | 2023-08-29 |
| 11737283 | Method of forming a stack of non-planar capacitors including capacitors with non-linear polar material and linear dielectric for common mode compensation in a memory bit-cell | Rajeev Kumar Dokania, Noriyuki Sato, Tanay Gosavi, Amrita Mathuriya | 2023-08-22 |
| 11735245 | Read scheme for multi-element gain ferroelectric memory bit-cell with plate-line parallel to word-line to minimize read or write disturb effects | Rajeev Kumar Dokania, Amrita Mathuriya | 2023-08-22 |
| 11729995 | Common mode compensation for non-linear polar material 1TnC memory bit-cell | Rajeev Kumar Dokania, Noriyuki Sato, Tanay Gosavi, Amrita Mathuriya | 2023-08-15 |
| 11729991 | Common mode compensation for non-linear polar material based differential memory bit-cell | Rajeev Kumar Dokania, Noriyuki Sato, Tanay Gosavi, Amrita Mathuriya | 2023-08-15 |
| 11727260 | Applications of back-end-of-line (BEOL) capacitors in compute-in-memory (CIM) circuits | Abhishek A. Sharma, Jack T. Kavalieros, Ian A. Young, Ram Krishnamurthy, Uygar E. Avci +7 more | 2023-08-15 |
| 11721690 | Method of adjusting threshold of a ferroelectric capacitive-input circuit | Amrita Mathuriya, Rafael Rios, Ikenna Odinaka, Rajeev Kumar Dokania | 2023-08-08 |
| 11716858 | Ferroelectric device film stacks with texturing layer which is part of a bottom electrode and a barrier, and method of forming such | Niloy Mukherjee, Ramamoorthy Ramesh, James David Clarkson, FNU Atiquzzaman, Gabriel Antonio Paulius Velarde +1 more | 2023-08-01 |