Issued Patents All Time
Showing 201–225 of 400 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11641747 | Integration of a ferroelectric memory device with a transistor | Gaurav Thareja, Rajeev Kumar Dokania, Ramamoorthy Ramesh, Amrita Mathuriya | 2023-05-02 |
| 11641205 | Reset mechanism for a chain of majority or minority gates having paraelectric material | Amrita Mathuriya, Rafael Rios, Ikenna Odinaka, Rajeev Kumar Dokania | 2023-05-02 |
| 11637090 | Method of forming a 3D stacked compute and memory | Rajeev Kumar Dokania, Amrita Mathuriya, Ramamoorthy Ramesh | 2023-04-25 |
| 11621391 | Antiferromagnet based spin orbit torque memory device | Chia-Ching Lin, Tanay Gosavi, Dmitri E. Nikonov, Kaan Oguz, Ian A. Young | 2023-04-04 |
| 11616507 | Ferroelectric based latch | Yuan-Sheng Fang, Robert Menezes, Rajeev Kumar Dokania, Ramamoorthy Ramesh, Amrita Mathuriya | 2023-03-28 |
| 11610620 | Pulsing scheme for a 1TNC ferroelectric memory bit-cell with plate-line parallel to bit-line to minimize read or write disturb effects | Rajeev Kumar Dokania, Amrita Mathuriya | 2023-03-21 |
| 11610619 | Pulsing scheme for a 1TNC ferroelectric memory bit-cell with plate-line parallel to word-line to minimize read or write disturb effects | Rajeev Kumar Dokania, Amrita Mathuriya | 2023-03-21 |
| 11611345 | NAND based sequential circuit with ferroelectric or paraelectric material | Amrita Mathuriya, Ikenna Odinaka, Rajeev Kumar Dokania, Rafael Rios | 2023-03-21 |
| 11605413 | Reading scheme for multi-element gain ferroelectric memory bit-cell with plate-lines parallel to a bit-line and with individual switches on the plate-lines of the bit-cell | Rajeev Kumar Dokania, Amrita Mathuriya | 2023-03-14 |
| 11605411 | Method of forming stacked ferroelectric planar capacitors in a memory bit-cell | Rajeev Kumar Dokania, Noriyuki Sato, Tanay Gosavi, Pratyush Pandey, Debo Olaosebikan +1 more | 2023-03-14 |
| 11600659 | Cross-point magnetic random access memory with piezoelectric selector | Dmitri E. Nikonov, Ian A. Young | 2023-03-07 |
| 11594624 | Transistor structures formed with 2DEG at complex oxide interfaces | Dmitri E. Nikonov, Chia-Ching Lin, Tanay Gosavi, Uygar E. Avci, Ian A. Young | 2023-02-28 |
| 11594270 | Perpendicular spin injection via spatial modulation of spin orbit coupling | Tanay Gosavi, Chia-Ching Lin, Dmitri E. Nikonov, Christopher J. Wiegand, Ian A. Young | 2023-02-28 |
| 11594673 | Two terminal spin orbit memory devices and methods of fabrication | Noriyuki Sato, Angeline Smith, Tanay Gosavi, Kaan Oguz, Kevin P. O'Brien +8 more | 2023-02-28 |
| 11581417 | Improper ferroelectric active and passive devices | Uygar E. Avci, Sou-Chi Chang, Ian A. Young | 2023-02-14 |
| 11575083 | Insertion layer between spin hall effect or spin orbit torque electrode and free magnet for improved magnetic memory | Tanay Gosavi, Kaan Oguz, Ian A. Young, Dmitri E. Nikonov, Chia-Ching Lin | 2023-02-07 |
| 11574666 | Spin orbit torque memory devices and methods of fabrication | Tanay Gosavi, Chia-Ching Lin, Kaan Oguz, Ian A. Young | 2023-02-07 |
| 11557717 | Transition metal dichalcogenide based spin orbit torque memory device with magnetic insulator | Chia-Ching Lin, Tanay Gosavi, Dmitri E. Nikonov, Ian A. Young | 2023-01-17 |
| 11552180 | Antiferroelectric perovskite gate oxide for transistor applications | Uygar E. Avci, Seiyon Kim, Ian A. Young | 2023-01-10 |
| 11545979 | Compare logic based sequential circuit with ferroelectric or paraelectric material | Amrita Mathuriya, Ikenna Odinaka, Rajeev Kumar Dokania, Rafael Rios | 2023-01-03 |
| 11545204 | Non-linear polar material based memory bit-cell with multi-level storage by applying different voltage levels | Rajeev Kumar Dokania, Noriyuki Sato, Tanay Gosavi, Pratyush Pandey, Debo Olaosebikan +1 more | 2023-01-03 |
| 11538514 | Writing scheme for 1TnC ferroelectric memory bit-cell with plate-lines parallel to a bit-line and with individual switches on the plate-lines of the bit-cell | Rajeev Kumar Dokania, Amrita Mathuriya | 2022-12-27 |
| 11539368 | Majority logic gate with input paraelectric capacitors | Rafael Rios, Ikenna Odinaka, Robert Menezes, Rajeev Kumar Dokania, Ramamoorthy Ramesh +1 more | 2022-12-27 |
| 11532635 | High-density low voltage multi-element ferroelectric gain memory bit-cell with pillar capacitors | Rajeev Kumar Dokania, Noriyuki Sato, Tanay Gosavi, Pratyush Pandey, Debo Olaosebikan +1 more | 2022-12-20 |
| 11532344 | Reading scheme for 1TNC ferroelectric memory bit-cell with plate-line parallel to bit-line and with individual switches on plate-lines of the bit-cell | Rajeev Kumar Dokania, Amrita Mathuriya | 2022-12-20 |