Issued Patents All Time
Showing 25 most recent of 251 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10991635 | Multiple chip bridge connector | Dale Curtis McHerron, Kamal K. Sikka, Joshua M. Rubin, Ravi K. Bonam, William J. Starke +1 more | 2021-04-27 |
| 10804166 | Porous silicon relaxation medium for dislocation free CMOS devices | Kangguo Cheng, Jeehwan Kim, Juntao Li, Devendra K. Sadana | 2020-10-13 |
| 10741554 | Third type of metal gate stack for CMOS devices | Sameer H. Jain, Viraj Y. Sardesai, Keith H. Tabakman | 2020-08-11 |
| 10707224 | FinFET vertical flash memory | Arvind Kumar, Carl Radens | 2020-07-07 |
| 10707332 | FinFET with epitaxial source and drain regions and dielectric isolated channel region | Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek, Soon-Cheon Seo | 2020-07-07 |
| 10600877 | Fully depleted SOI device for reducing parasitic back gate capacitance | Kangguo Cheng | 2020-03-24 |
| 10586799 | Multiple-bit electrical fuses | Kangguo Cheng | 2020-03-10 |
| 10559662 | Hybrid aspect ratio trapping | Kangguo Cheng, Hong He, Juntao Li | 2020-02-11 |
| 10541177 | Porous silicon relaxation medium for dislocation free CMOS devices | Kangguo Cheng, Jeehwan Kim, Juntao Li, Devendra K. Sadana | 2020-01-21 |
| 10522661 | Integrated strained stacked nanosheet FET | Kangguo Cheng, Juntao Li, Xin Miao | 2019-12-31 |
| 10388795 | Vertical transistor including controlled gate length and a self-aligned junction | Kangguo Cheng | 2019-08-20 |
| 10283602 | Fully depleted SOI device for reducing parasitic back gate capacitance | Kangguo Cheng | 2019-05-07 |
| 10283625 | Integrated strained stacked nanosheet FET | Kangguo Cheng, Juntao Li, Xin Miao | 2019-05-07 |
| 10262996 | Third type of metal gate stack for CMOS devices | Sameer H. Jain, Viraj Y. Sardesai, Keith H. Tabakman | 2019-04-16 |
| 10242980 | Semiconductor fin isolation by a well trapping fin portion | Henry K. Utomo, Kangguo Cheng, Ravikumar Ramachandran, Huiling Shang, Reinaldo Vega | 2019-03-26 |
| 10229857 | Porous silicon relaxation medium for dislocation free CMOS devices | Kangguo Cheng, Jeehwan Kim, Juntao Li, Devendra K. Sadana | 2019-03-12 |
| 10204836 | Porous silicon relaxation medium for dislocation free CMOS devices | Kangguo Cheng, Jeehwan Kim, Juntao Li, Devendra K. Sadana | 2019-02-12 |
| 10170628 | Method for forming an extremely thin silicon-on-insulator (ETSOI) device having reduced parasitic capacitance and contact resistance due to wrap-around structure of source/drain regions | Kangguo Cheng | 2019-01-01 |
| 10170372 | FINFET CMOS with Si NFET and SiGe PFET | Kangguo Cheng, Jeehwan Kim | 2019-01-01 |
| 10141320 | Multiple-bit electrical fuses | Kangguo Cheng | 2018-11-27 |
| 10084067 | FinFET with epitaxial source and drain regions and dielectric isolated channel region | Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek, Soon-Cheon Seo | 2018-09-25 |
| 10062615 | Stacked nanowire devices | Kangguo Cheng, Juntao Li | 2018-08-28 |
| 10002876 | FinFET vertical flash memory | Arvind Kumar, Carl Radens | 2018-06-19 |
| 9997618 | Integrated strained stacked nanosheet FET | Kangguo Cheng, Juntao Li, Xin Miao | 2018-06-12 |
| 9997606 | Fully depleted SOI device for reducing parasitic back gate capacitance | Kangguo Cheng | 2018-06-12 |