QY

Qingyun Yang

IBM: 13 patents #8,581 of 70,183Top 15%
TL Tokyo Electron Limited: 4 patents #1,723 of 5,567Top 35%
Overall (All Time): #313,033 of 4,157,543Top 8%
15
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
12057322 Methods for etching metal films using plasma processing Nicholas Joy, Devi Koty, Nathan P. Marchack, Sebastian U. Engelmann 2024-08-06
11844290 Plasma co-doping to reduce the forming voltage in resistive random access memory (ReRAM) devices Devi Koty, Hongwen Yan, Hiroyuki Miyazoe, Takashi Ando, Marinus Hopstaken 2023-12-12
11258012 Oxygen-free plasma etching for contact etching of resistive random access memory Devi Koty, Hiroyuki Miyazoe, Takashi Ando, Eduard A. Cartier, Vijay Narayanan +1 more 2022-02-22
10651372 Process for patterning a magnetic tunnel junction 2020-05-12
9105741 Method of replacement source/drain for 3D CMOS transistors Kevin K. Chan, Jinghong Li, Dae-Gyu Park, Xinhui Wang, Yun-Yu Wang 2015-08-11
8481389 Method of removing high-K dielectric layer on sidewalls of gate structure Ying Zhang, Hongwen Yan 2013-07-09
8445948 Gate patterning of nano-channel devices Nicholas C. M. Fuller, Sarunya Bangsaruntip, Guy M. Cohen, Sebastian U. Engelmann, Lidija Sekaric +1 more 2013-05-21
7816275 Gate patterning of nano-channel devices Nicholas C. M. Fuller, Sarunya Bangsaruntip, Guy M. Cohen, Sebastian U. Engelmann, Lidija Sekaric +1 more 2010-10-19
7435652 Integration schemes for fabricating polysilicon gate MOSFET and high-K dielectric metal gate MOSFET Tze-Chiang Chen, Bruce B. Doris, Rangarajan Jagannathan, Hongwen Yan, Ying Zhang 2008-10-14
6960510 Method of making sub-lithographic features Sadanand V. Deshpande, Toshiharu Furukawa, David V. Horak, Wesley C. Natzle, Akihisa Sekiguchi +1 more 2005-11-01
6864041 Gate linewidth tailoring and critical dimension control for sub-100 nm devices using plasma etching Jeffrey J. Brown, Sadanand V. Deshpande, David V. Horak, Maheswaran Surendra, Len Yuan Tsou +2 more 2005-03-08
6828187 Method for uniform reactive ion etching of dual pre-doped polysilicon regions Joyce C. Liu, Len Yuan Tsou 2004-12-07
6703269 Method to form gate conductor structures of dual doped polysilicon Jeffrey J. Brown, Len Yuan Tsou 2004-03-09
6541320 Method to controllably form notched polysilicon gate structures Jeffrey J. Brown, Richard S. Wise, Hongwen Yan, Chienfan Yu 2003-04-01
6509219 Fabrication of notched gates by passivating partially etched gate sidewalls and then using an isotropic etch Len Yuan Tsou, Hongwen Yan, Chienfan Yu 2003-01-21