Issued Patents All Time
Showing 1–25 of 27 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12261110 | Electronic assembly having multiple substrate segments | Shishuang Sun, Ganesh Venkataramanan | 2025-03-25 |
| 11973004 | Mechanical architecture for a multi-chip module | Robert Y. Cao, Mitchell Heschke, Shishuang Sun, Vijaykumar Krithivasan | 2024-04-30 |
| 11967528 | Structure and method for fabricating a computing system with an integrated voltage regulator module | Vidhya Ramachandran, Jun Zhai, Chonghua Zhong, Kunzhong Hu, Shawn Searles +1 more | 2024-04-23 |
| 11901310 | Electronic assembly | Shishuang Sun, Ganesh Venkataramanan, William McGee, Steven Butler | 2024-02-13 |
| 11670548 | Structure and method for fabricating a computing system with an integrated voltage regulator module | Vidhya Ramachandran, Jun Zhai, Chonghua Zhong, Kunzhong Hu, Shawn Searles +1 more | 2023-06-06 |
| 11367680 | Electronic assembly having multiple substrate segments | Shishuang Sun, Ganesh Venkataramanan | 2022-06-21 |
| 11122678 | Packaged device having imbedded array of components | Vijaykumar Krithivasan, Jin Zhao, Steven Butler, Ganesh Venkataramanan, Yang Sun | 2021-09-14 |
| 11069665 | Trimmable banked capacitor | Vidhya Ramachandran, Chonghua Zhong, Jun Zhai, Long Huang, Rohan U. Mandrekar | 2021-07-20 |
| 10818632 | Structure and method for fabricating a computing system with an integrated voltage regulator module | Vidhya Ramachandran, Jun Zhai, Chonghua Zhong, Kunzhong Hu, Shawn Searles +1 more | 2020-10-27 |
| 10103138 | Dual-sided silicon integrated passive devices | Jun Zhai, Vidhya Ramachandran, Kunzhong Hu, Chonghua Zhong | 2018-10-16 |
| 9935076 | Structure and method for fabricating a computing system with an integrated voltage regulator module | Vidhya Ramachandran, Jun Zhai, Chonghua Zhong, Kunzhong Hu, Shawn Searles +1 more | 2018-04-03 |
| 9748227 | Dual-sided silicon integrated passive devices | Jun Zhai, Vidhya Ramachandran, Kunzhong Hu, Chonghua Zhong | 2017-08-29 |
| 9659907 | Double side mounting memory integration in thin low warpage fanout package | Jun Zhai, Kunzhong Hu, Chonghua Zhong, Se Young Yang | 2017-05-23 |
| 9633974 | System in package fan out stacking architecture and process flow | Jun Zhai, Kunzhong Hu, Kwan-Yu Lai, Chonghua Zhong, Se Young Yang | 2017-04-25 |
| 9318474 | Thermally enhanced wafer level fan-out POP package | Jun Zhai, Yizhang Yang | 2016-04-19 |
| 9236355 | EMI shielded wafer level fan-out pop package | Jun Zhai, Se Young Yang, Leland W. Lew | 2016-01-12 |
| 8957516 | Low cost and high performance flip chip package | Ken Zhonghua Wu, Matthew Kaufmann | 2015-02-17 |
| 8759974 | Solder joints with enhanced electromigration resistance | Pilin Liu, Charavanakumara Gurumurthy | 2014-06-24 |
| 8508054 | Enhanced bump pitch scaling | Matthew Kaufmann | 2013-08-13 |
| 8395051 | Doping of lead-free solder alloys and structures formed thereby | Charan Gurumurthy | 2013-03-12 |
| 8013444 | Solder joints with enhanced electromigration resistance | Pilin Liu, Charavanakumara Gurumurthy | 2011-09-06 |
| 7791185 | Pin grid array package substrate including pins having curved pin heads | — | 2010-09-07 |
| 7790598 | System, apparatus, and method for advanced solder bumping | Christopher Bahr, Ravindra Tanikella, Charan Gurumurthy | 2010-09-07 |
| 7569471 | Method of providing mixed size solder bumps on a substrate using a solder delivery head | John S. Guzek | 2009-08-04 |
| 7517788 | System, apparatus, and method for advanced solder bumping | Christopher Bahr, Ravindra Tanikella, Charan Gurumurthy | 2009-04-14 |