Issued Patents All Time
Showing 1–19 of 19 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10297510 | Sidewall image transfer process for multiple gate width patterning | Soon-Cheon Seo, Fee Li Lie | 2019-05-21 |
| 10283505 | Dummy gate used as interconnection and method of making the same | Wenhui Wang, Ryan Ryoung-Han Kim, Jason R. Cantone, Lei Sun, Seowoo Nam | 2019-05-07 |
| 10181420 | Devices with chamfer-less vias multi-patterning and methods for forming chamfer-less vias | Jason E. Stephens, David Permana, Guillaume Bouche, Andy Wei, Mark A. Zaleski +6 more | 2019-01-15 |
| 9842741 | Removal of semiconductor growth defects | Soon-Cheon Seo | 2017-12-12 |
| 9653571 | Freestanding spacer having sub-lithographic lateral dimension and method of forming same | Hsueh-Chung Chen, Su Chen Fan, Dong-Kwon Kim, Sean Lian, Fee Li Lie | 2017-05-16 |
| 9653573 | Replacement metal gate including dielectric gate material | Sivananda K. Kanakasabapathy, Sanjay C. Mehta, Soon-Cheon Seo, Raghavasimhan Sreenivasan | 2017-05-16 |
| 9595478 | Dummy gate used as interconnection and method of making the same | Wenhui Wang, Ryan Ryoung-Han Kim, Jason R. Cantone, Lei Sun, Seowoo Nam | 2017-03-14 |
| 9496257 | Removal of semiconductor growth defects | Soon-Cheon Seo | 2016-11-15 |
| 9466505 | Methods of patterning features having differing widths | Soon-Cheon Seo, Ryan O. Jung | 2016-10-11 |
| 9449835 | Methods of forming features having differing pitch spacing and critical dimensions | Ryan Ryoung-Han Kim | 2016-09-20 |
| 9431264 | Methods of forming integrated circuits and multiple critical dimension self-aligned double patterning processes | Young-joon Moon, Ryan Ryoung-Han Kim | 2016-08-30 |
| 9214360 | Methods of patterning features having differing widths | Soon-Cheon Seo, Ryan O. Jung | 2015-12-15 |
| 9209038 | Methods for fabricating integrated circuits using self-aligned quadruple patterning | Jason R. Cantone, Ryan Ryoung-Han Kim | 2015-12-08 |
| 9209037 | Methods for fabricating integrated circuits including selectively forming and removing fin structures | Jason R. Cantone, Jin Cho, Ryan Ryoung-Han Kim | 2015-12-08 |
| 9184263 | Methods of forming gate structures for semiconductor devices using a replacement gate technique and the resulting devices | Xiuyu Cai, Ajey Poovannummoottil Jacob, Daniel T. Pham, Mark V. Raymond, Christopher M. Prindle +2 more | 2015-11-10 |
| 9045933 | Energy-efficient smart window system | Kanti Jain | 2015-06-02 |
| 8871649 | Methods of forming trench/hole type features in a layer of material of an integrated circuit product | Yoshinori Matsui, Chiahsun Tseng | 2014-10-28 |
| 8716094 | FinFET formation using double patterning memorization | Chang Seo Park, Jin Cho | 2014-05-06 |
| 7940457 | Energy-efficient optoelectronic smart window | Kanti Jain, Yoon-Soo Han | 2011-05-10 |