Issued Patents All Time
Showing 25 most recent of 41 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9397203 | Lateral silicon-on-insulator bipolar junction transistor process and structure | John Z. Colt, Jr., John J. Ellis-Monaghan, Steven M. Shank | 2016-07-19 |
| 9244946 | Data mining shape based data | Maroun Kassab, Adam E. Trojanowski | 2016-01-26 |
| 9235601 | Data mining shape based data | Maroun Kassab, Adam E. Trojanowski | 2016-01-12 |
| 9059230 | Lateral silicon-on-insulator bipolar junction transistor process and structure | John Z. Colt, Jr., John J. Ellis-Monaghan, Steven M. Shank | 2015-06-16 |
| 8571299 | Identifying defects | Mohammed Fazil Fayaz, Julie L. Lee, Maroun Kassab | 2013-10-29 |
| 8566059 | Insertion of faults in logic model used in simulation | Rao H. Desineni, Maroun Kassab, Mary P. Kusko | 2013-10-22 |
| 8136082 | Method for testing integrated circuits | Rao H. Desineni, Maroun Kassab, Franco Motika | 2012-03-13 |
| 7971176 | Method for testing integrated circuits | Rao H. Desineni, Maroun Kassab, Franco Motika | 2011-06-28 |
| 7898045 | Passive electrically testable acceleration and voltage measurement devices | Toshiharu Furukawa, Mark C. Hakey, Steven J. Holmes, David V. Horak, Charles W. Koburger, III | 2011-03-01 |
| 7895545 | Methods for designing a product chip a priori for design subsetting, feature analysis, and yield learning | John M. Cohn, Gustavo E. Tellez | 2011-02-22 |
| 7895487 | Scan chain diagnostics using logic paths | Leendert M. Huisman | 2011-02-22 |
| 7853848 | System and method for signature-based systematic condition detection and analysis | Rao H. Desineni, Maroun Kassab | 2010-12-14 |
| 7629192 | Passive electrically testable acceleration and voltage measurement devices | Toshiharu Furukawa, Mark C. Hakey, Steven J. Holmes, David V. Horak, Charles W. Koburger, III | 2009-12-08 |
| 7596736 | Iterative process for identifying systematics in data | Maroun Kassab | 2009-09-29 |
| 7484423 | Integrated carbon nanotube sensors | Mark C. Hakey, Mark E. Masters, David P. Vallett | 2009-02-03 |
| 7434130 | Using clock gating or signal gating to partition a device for fault isolation and diagnostic data collection | Leendert M. Huisman, William V. Huott, Franco Motika | 2008-10-07 |
| 7428675 | Testing using independently controllable voltage islands | Anne Elizabeth Gattiker, Phil Nigh, Steven F. Oakland, Jody VanHorn, Paul S. Zuchowski | 2008-09-23 |
| 7397263 | Sensor differentiated fault isolation | Kevin L. Condon, Theodore M. Levin, David P. Vallett | 2008-07-08 |
| 7285860 | Method and structure for defect monitoring of semiconductor devices using power bus wiring grids | John M. Cohn, Thomas G. Sopchak, David P. Vallett | 2007-10-23 |
| 7247877 | Integrated carbon nanotube sensors | Mark C. Hakey, Mark E. Masters, David P. Vallett | 2007-07-24 |
| 7239167 | Utilizing clock shield as defect monitor | John M. Cohn, Thomas G. Sopchak, David P. Vallett | 2007-07-03 |
| 7240261 | Scan chain diagnostics using logic paths | Leendert M. Huisman | 2007-07-03 |
| 7230335 | Inspection methods and structures for visualizing and/or detecting specific chip structures | Jerome L. Cann, Steven J. Holmes, Leendert M. Huisman, Cherie R. Kagan, Paul William Pastel +2 more | 2007-06-12 |
| 7202689 | Sensor differentiated fault isolation | Kevin L. Condon, Theodore M. Levin, David P. Vallett | 2007-04-10 |
| 7194706 | Designing scan chains with specific parameter sensitivities to identify process defects | James W. Adkisson, Greg Bazan, John M. Cohn, Matthew S. Grady, Leendert M. Huisman +5 more | 2007-03-20 |