Issued Patents All Time
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9806014 | Interposer with beyond reticle field conductor pads | Michael Alfano, Bryan Black, Michael Z. Su, Julius Din, Anwar Kashem | 2017-10-31 |
| 9627281 | Semiconductor chip with thermal interface tape | Seth Prejean, Dales Morrison Kent, Ronnie Brandon, Gamal Refai-Ahmed, Michael Z. Su +2 more | 2017-04-18 |
| 8850278 | Fault tolerant scannable glitch latch | Kevin M. Gillespie, Dwight K. Elvey, Harry Ray Fair, III | 2014-09-30 |
| 8451014 | Die stacking, testing and packaging for yield | Bryan Black | 2013-05-28 |
| 7228474 | Semiconductor device and method and apparatus for testing such a device | Emrys J. Williams, Kenneth House | 2007-06-05 |
| 7000164 | Method for scan testing and clocking dynamic domino circuits in VLSI systems using level sensitive latches and edge triggered flip flops | David Greenhill, Ban Wong | 2006-02-14 |
| 6996491 | Method and system for monitoring and profiling an integrated circuit die temperature | Spencer Gold, Claude Gauthier, Steven R. Boyle, Kenneth House | 2006-02-07 |
| 6907556 | Scanable R-S glitch latch for dynamic circuits | — | 2005-06-14 |
| 6785855 | Implementation of an assertion check in ATPG models | Aiteen Zhang | 2004-08-31 |
| 6720813 | Dual edge-triggered flip-flop design with asynchronous programmable reset | Gin Yee, Pradeep Trivedi | 2004-04-13 |
| 6700946 | System and method for automatic generation of an at-speed counter | Kamran Zarrineh, Kenneth House | 2004-03-02 |
| 6594194 | Memory array with common word line | Spencer Gold | 2003-07-15 |
| 6570407 | Scannable latch for a dynamic circuit | Junji Sugisawa, Larry Kan, David Greenhill | 2003-05-27 |
| 6487702 | Automated decoupling capacitor insertion | Chen-Li Lin, Joel Grinberg | 2002-11-26 |