Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7039843 | Modeling custom scan flops in level sensitive scan design | — | 2006-05-02 |
| 6785855 | Implementation of an assertion check in ATPG models | Joseph Siegel | 2004-08-31 |
AZ
Aiteen Zhang
Overall (All Time): #2,168,502 of 4,157,543Top 55%
2
Patents All Time