Issued Patents All Time
Showing 1–25 of 33 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10395981 | Semiconductor device including a leveling dielectric fill material | Jeremy A. Wahl | 2019-08-27 |
| 10224251 | Semiconductor devices and manufacturing techniques for reduced aspect ratio of neighboring gate electrode lines | Peter Baars, Gunter Grasshoff | 2019-03-05 |
| 10048311 | Detection of gate-to-source/drain shorts | Uwe Dersch, Ricardo P. Mikalo | 2018-08-14 |
| 9960184 | FDSOI-capacitor | Jan Hoentschel, Peter Baars | 2018-05-01 |
| 9735174 | FDSOI—capacitor | Jan Hoentschel, Peter Baars | 2017-08-15 |
| 9673115 | Test structures and method of forming an according test structure | Dieter Lipp, Stefan Richter | 2017-06-06 |
| 9627409 | Semiconductor device with thin-film resistor | Andrei Sidelnicov, Maciej Wiatr | 2017-04-18 |
| 9608003 | Integrated circuit product with bulk and SOI semiconductor devices | Peter Baars, Jan Hoentschel | 2017-03-28 |
| 9553046 | E-fuse in SOI configuration | Jan Hoentschel, Peter Baars | 2017-01-24 |
| 9553030 | Method of manufacturing P-channel FET device with SiGe channel | Peter Baars | 2017-01-24 |
| 9502564 | Fully depleted device with buried insulating layer in channel region | Peter Baars, Jan Hoentschel | 2016-11-22 |
| 9466685 | Semiconductor structure including at least one electrically conductive pillar, semiconductor structure including a contact contacting an outer layer of an electrically conductive structure and method for the formation thereof | Peter Baars, Thorsten Kammler | 2016-10-11 |
| 9443871 | Cointegration of bulk and SOI semiconductor devices | Peter Baars, Jan Hoentschel | 2016-09-13 |
| 9425189 | Compact FDSOI device with Bulex contact extending through buried insulating layer adjacent gate structure for back-bias | Peter Baars | 2016-08-23 |
| 9391156 | Embedded capacitor | Peter Baars, Jan Hoentschel | 2016-07-12 |
| 9385232 | FD devices in advanced semiconductor techniques | Peter Baars, Jan Hoentschel | 2016-07-05 |
| 9111756 | Integrated circuits with protected resistors and methods for fabricating the same | Joachim Patzer | 2015-08-18 |
| 9023709 | Top corner rounding by implant-enhanced wet etching | Marco Lepper, Werner Graf | 2015-05-05 |
| 8889022 | Methods of forming asymmetric spacers on various structures on integrated circuit products | Joachim Patzer | 2014-11-18 |
| 8138538 | Interconnect structure for semiconductor devices | Gouri Sankar Kar, Martin Popp, Lars Heineck, Peter Lahnor, Arnd Scholz +8 more | 2012-03-20 |
| 7754579 | Method of forming a semiconductor device | Kimberly Wilson, Rolf Weis, Phillip Stopford, Frank Ludwig | 2010-07-13 |
| 7605032 | Method for producing a trench transistor and trench transistor | Richard Luyken, Martin Popp, Till Schloesser, Marc Strasser, Rolf Weis | 2009-10-20 |
| 7261829 | Method for masking a recess in a structure having a high aspect ratio | Dirk Efferenn | 2007-08-28 |
| 7125778 | Method for fabricating a self-aligning mask | Dirk Efferenn, Ulrike Grüning Von Schwerin, Jorg Radecker, Andreas Wich-Glasen | 2006-10-24 |
| 7084029 | Method for fabricating a hole trench storage capacitor in a semiconductor substrate, and hole trench storage capacitor | Srivatsa Kundalgurki, Dietmar Temmler, Joerg Wiedemann | 2006-08-01 |