Issued Patents All Time
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11714950 | Automated timing closure on circuit designs | Veeresh Pratap Singh, Meghraj Kalase, John Blaine, Srinivasan Dasasathyan, Padmini Gopalakrishnan +4 more | 2023-08-01 |
| 11709521 | Synchronous clock domain crossing skew optimization and multi-clock buffer (MBUFG) | Frank Mueller, Thomas O. Satter, Mehrdad Eslami Dehkordi, Garik Mkrtchyan, Satish B. Sivaswamy +2 more | 2023-07-25 |
| 11681846 | Sub-FPGA level compilation platform with adjustable dynamic region for emulation/prototyping designs | Xiaojian Yang, Dinesh D. Gaitonde, Amit Gupta | 2023-06-20 |
| 10867093 | System and method for an electronic design tool providing automated guidance and interface for circuit design processing | John Blaine, Srinivasan Dasasathyan, Meghraj Kalase, Veeresh Pratap Singh, Satish Bachina +4 more | 2020-12-15 |
| 10242150 | Circuit design implementation using control-set based merging and module-based replication | Sabyasachi Das, Xiaojian Yang, Niyati Shah, Govinda Keshavdas | 2019-03-26 |
| 9836568 | Programmable integrated circuit design flow using timing-driven pipeline analysis | Ilya K. Ganusov, Aaron Ng, Ronald E. Plyler, Sabyasachi Das | 2017-12-05 |
| 8549454 | System and method for automated configuration of design constraints | Raymond Kong, David A. Knol, Dinesh K. Monga | 2013-10-01 |