Issued Patents All Time
Showing 1–22 of 22 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12417994 | Semiconductor chip having stepped conductive pillars | Suming Hu | 2025-09-16 |
| 11955447 | Semiconductor chip having stepped conductive pillars | Suming Hu | 2024-04-09 |
| 11315883 | Integrated circuit product customizations for identification code visibility | Suming Hu, Roden R. Topacio, Jianguo Li, Andrew Kwan Wai Leung | 2022-04-26 |
| 10903168 | Multi-RDL structure packages and methods of fabricating the same | Milind S. Bhagavat, Lei Fu | 2021-01-26 |
| 10672712 | Multi-RDL structure packages and methods of fabricating the same | Milind S. Bhagavat, Lei Fu | 2020-06-02 |
| 7405946 | Ball grid array assignment | Jeffrey A. Hall | 2008-07-29 |
| 7345245 | Robust high density substrate design for thermal cycling reliability | Anand Govind, Zafer Kutlu | 2008-03-18 |
| 7319272 | Ball assignment system | Arun Ramakrishnan, Aritharan Thurairajaratnam, Leah M. Miller | 2008-01-15 |
| 7105926 | Routing scheme for differential pairs in flip chip substrates | Arun Ramakrishnan, Anand Govind | 2006-09-12 |
| 7081672 | Substrate via layout to improve bias humidity testing reliability | Anand Govind, Aritharan Thurairajaratnam | 2006-07-25 |
| 7051434 | Designing a ball assignment for a ball grid array package | Leah M. Miller | 2006-05-30 |
| 6946866 | Measurement of package interconnect impedance using tester and supporting tester | Aritharan Thurairajaratnam, Mohan R. Nagar, Anand Govind | 2005-09-20 |
| 6825066 | Stiffener design | Yogendra Ranade, Anand Govind, Kumar Nagarajan, Aritharan Thurairajaratnam | 2004-11-30 |
| 6762366 | Ball assignment for ball grid array package | Leah M. Miller, Edwin M. Fulcher | 2004-07-13 |
| 6671865 | High density input output | Anwar Ali, Edwin M. Fulcher | 2003-12-30 |
| 6531932 | Microstrip package having optimized signal line impedance control | Anand Govind, Aritharan Thurairajaratnam | 2003-03-11 |
| 6479319 | Contact escape pattern | Leonard L. Mora | 2002-11-12 |
| 6459049 | High density signal routing | Leah M. Miller, Edwin M. Fulcher, Aritharan Thurairajaratnam | 2002-10-01 |
| 6407462 | Irregular grid bond pad layout arrangement for a flip chip package | Nikon Banouvong | 2002-06-18 |
| 6150729 | Routing density enhancement for semiconductor BGA packages and printed wiring boards | — | 2000-11-21 |
| 6115910 | Misregistration fidutial | — | 2000-09-12 |
| 6114761 | Thermally-enhanced flip chip IC package with extruded heatspreader | Atila Mertol, Zeki Z. Celik, Zafer Kutlu | 2000-09-05 |