Issued Patents All Time
Showing 25 most recent of 37 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12148715 | Electronic device including a substrate, a structure, and an adhesive and a process of forming the same | — | 2024-11-19 |
| 11942405 | Semiconductor package assembly using a passive device as a standoff | Jianguo Li | 2024-03-26 |
| 11335659 | Semiconductor chip with patterned underbump metallization and polymer film | Suming Hu, Yip Seng Low | 2022-05-17 |
| 11315883 | Integrated circuit product customizations for identification code visibility | Suming Hu, Farshad Ghahghahi, Jianguo Li, Andrew Kwan Wai Leung | 2022-04-26 |
| 10431533 | Circuit board with constrained solder interconnect pads | Andrew KW Leung | 2019-10-01 |
| 10403589 | Interconnect etch with polymer layer edge protection | — | 2019-09-03 |
| 9728518 | Interconnect etch with polymer layer edge protection | — | 2017-08-08 |
| 9576923 | Semiconductor chip with patterned underbump metallization and polymer film | Suming Hu, Yip Seng Low | 2017-02-21 |
| 9318457 | Methods of fabricating semiconductor chip solder structures | Neil McLellan | 2016-04-19 |
| 9209106 | Thermal management circuit board for stacked semiconductor chip device | Xiao Ling Shi, Suming Hu, Liane Martinez, Terence Cheung | 2015-12-08 |
| 9142520 | Methods of fabricating semiconductor chip solder structures | Neil McLellan | 2015-09-22 |
| 9059159 | Routing layer for mitigating stress in a semiconductor die | Gabriel Wong | 2015-06-16 |
| 9035471 | Routing layer for mitigating stress in a semiconductor die | Gabriel Wong | 2015-05-19 |
| 8927344 | Die substrate with reinforcement structure | Adam Zbrzezny | 2015-01-06 |
| 8847383 | Integrated circuit package strip with stiffener | Neil McLellan, Vincent Chan | 2014-09-30 |
| 8772083 | Solder mask with anchor structures | Andrew KW Leung, Yu-Ling Hsieh, Yip Seng Low | 2014-07-08 |
| 8664777 | Routing layer for mitigating stress in a semiconductor die | Gabriel Wong | 2014-03-04 |
| 8647974 | Method of fabricating a semiconductor chip with supportive terminal pad | Michael Z. Su, Neil McLellan | 2014-02-11 |
| 8642463 | Routing layer for mitigating stress in a semiconductor die | Gabriel Wong | 2014-02-04 |
| 8637983 | Face-to-face (F2F) hybrid structure for an integrated circuit | Liane Martinez, Yip Seng Low | 2014-01-28 |
| 8633599 | Semiconductor chip with underfill anchors | Neil McLellan | 2014-01-21 |
| 8389340 | Methods of forming semiconductor chip underfill anchors | Neil McLellan | 2013-03-05 |
| 8378471 | Semiconductor chip bump connection apparatus and method | Vincent Chan, Fan Yeung | 2013-02-19 |
| 8313984 | Die substrate with reinforcement structure | Adam Zbrzezny | 2012-11-20 |
| 8298945 | Method of manufacturing substrates having asymmetric buildup layers | Andrew KW Leung, Liane Martinez, Yip Seng Low | 2012-10-30 |