Issued Patents All Time
Showing 1–25 of 25 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8350375 | Flipchip bump patterns for efficient I-mesh power distribution schemes | Kalyan Doddapaneni, Wilson Wai Sing Leung | 2013-01-08 |
| 8151237 | Disabling unused IO resources in platform-based integrated circuits | Julie Beatty, Kalyan Doddapaneni | 2012-04-03 |
| 8115321 | Separate probe and bond regions of an integrated circuit | Kalyan Doddapaneni, Gokulnath Sulur, Wilson Wai Sing Leung, Tauman T. Lau | 2012-02-14 |
| 7863716 | Method and apparatus of power ring positioning to minimize crosstalk | Tauman T. Lau, Kalyan Doddapaneni | 2011-01-04 |
| 7737564 | Power configuration method for structured ASICs | Tauman T. Lau, Kalyan Doddapaneni | 2010-06-15 |
| 7569472 | Method and apparatus of power ring positioning to minimize crosstalk | Tauman T. Lau, Kalyan Doddapaneni | 2009-08-04 |
| 7554133 | Pad current splitting | Nenad Miladinovic, Kalyan Doddapaneni | 2009-06-30 |
| 7430730 | Disabling unused IO resources in platform-based integrated circuits | Julie Beatty, Kalyan Doddapaneni | 2008-09-30 |
| 7328417 | Cell-based method for creating slotted metal in semiconductor designs | Tauman T. Lau, Kalyan Doddapaneni | 2008-02-05 |
| 7117467 | Methods for optimizing package and silicon co-design of integrated circuit | Stan Mihelcic, James G. Monthie | 2006-10-03 |
| 7107561 | Method of sizing via arrays and interconnects to reduce routing congestion in flip chip integrated circuits | Wei-Ming Huang | 2006-09-12 |
| 7075179 | System for implementing a configurable integrated circuit | Julie Beatty, Kalyan Doddapaneni | 2006-07-11 |
| 6998638 | Test structure for detecting bonding-induced cracks | Qwai H. Low, Ramaswamy Ranganathan, Tauman T. Lau | 2006-02-14 |
| 6836026 | Integrated circuit design for both input output limited and core limited integrated circuits | Tauman T. Lau, Max M. Young | 2004-12-28 |
| 6815812 | Direct alignment of contacts | Ken Nguyen, Max M. Yeung | 2004-11-09 |
| 6798069 | Integrated circuit having adaptable core and input/output regions with multi-layer pad trace conductors | Tauman T. Lau, Kalyan Doddapaneni | 2004-09-28 |
| 6784102 | Laterally interconnecting structures | Max M. Yeung, Tauman T. Lau | 2004-08-31 |
| 6781228 | Donut power mesh scheme for flip chip package | Hiroshi Ishikawa, Thomas Antisseril, Radoslav Ratchkov, Bo Shen, Prasad Subbarao +2 more | 2004-08-24 |
| 6781150 | Test structure for detecting bonding-induced cracks | Qwai H. Low, Ramaswamy Ranganathan, Tauman T. Lau | 2004-08-24 |
| 6768142 | Circuit component placement | Tauman T. Lau, Max M. Yeung, Ken Nguyen, Wei-Ming Huang | 2004-07-27 |
| 6704918 | Integrated circuit routing | Virendra Patel | 2004-03-09 |
| 6683476 | Contact ring architecture | Tauman T. Lau, Max M. Yeung | 2004-01-27 |
| 6671865 | High density input output | Farshad Ghahghahi, Edwin M. Fulcher | 2003-12-30 |
| 6657870 | Die power distribution system | Benjamin Mbouombouo, Max M. Yeung | 2003-12-02 |
| 6591410 | Six-to-one signal/power ratio bump and trace pattern for flip chip design | Mike Liang, Bing-Wei Yi | 2003-07-08 |