Issued Patents All Time
Showing 1–25 of 32 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10346283 | Dynamically identifying performance anti-patterns | Hitham Ahmed Assem Aly Salama, Nicholas Matthew Mitchell, Patrick J. O'Sullivan, Andres Omar Portillo Dominguez, Peter F. Sweeney | 2019-07-09 |
| 10176022 | Dynamically adapting a test workload to accelerate the identification of performance issues | Hitham Ahmed Assem Aly Salama, Nicholas Matthew Mitchell, Patrick J. O'Sullivan, Andres Omar Portillo Dominguez, Peter F. Sweeney | 2019-01-08 |
| 10078571 | Rule-based adaptive monitoring of application performance | Hitham Ahmed Assem Aly Salama, Nicholas Matthew Mitchell, Patrick J. O'Sullivan, Andres Omar Portillo Dominguez, Peter F. Sweeney | 2018-09-18 |
| 9823994 | Dynamically identifying performance anti-patterns | Hitham Ahmed Assem Aly Salama, Nicholas Matthew Mitchell, Patrick J. O'Sullivan, Andres Omar Portillo Dominguez, Peter F. Sweeney | 2017-11-21 |
| 8719548 | Method and system for efficient emulation of multiprocessor address translation on a multiprocessor | Ravi Nair, John Kevin Patrick O'Brien, Kathryn M. O'Brien, Peter Howland Oden, Daniel A. Prener +1 more | 2014-05-06 |
| 8627317 | Automatic identification of bottlenecks using rule-based expert knowledge | Matthew R. Arnold, Nicholas Matthew Mitchell | 2014-01-07 |
| 8589662 | Accepting or rolling back execution of instructions based on comparing predicted and actual dependency control signals | Michael K. Gschwind, Jude A. Rivers, Sumedh W. Sathaye, John-David Wellman, Victor Zyuban | 2013-11-19 |
| 8151092 | Control signal memoization in a multiple instruction issue microprocessor | Michael K. Gschwind, Jude A. Rivers, Sumedh W. Sathaye, John-David Wellman, Victor Zyuban | 2012-04-03 |
| 7979682 | Method and system for preventing livelock due to competing updates of prediction information | Vijayalakshmi Srinivasan | 2011-07-12 |
| 7971033 | Limiting entries in load issued premature part of load reorder queue searched to detect invalid retrieved values to between store safe and snoop safe pointers for the congruence class | Vijayalakshmi Srinivasan | 2011-06-28 |
| 7966478 | Limiting entries in load reorder queue searched for snoop check to between snoop peril and tail pointers | Vijayalakshmi Srinivasan | 2011-06-21 |
| 7953588 | Method and system for efficient emulation of multiprocessor address translation on a multiprocessor host | Ravi Nair, John Kevin Patrick O'Brien, Kathryn M. O'Brien, Peter Howland Oden, Daniel A. Prener +1 more | 2011-05-31 |
| 7865699 | Method and apparatus to extend the number of instruction bits in processors with fixed length instructions, in a manner compatible with existing code | Michael K. Gschwind, David Arnold Luick, Daniel A. Prener, Jude A. Rivers, Sumedh W. Sathaye +1 more | 2011-01-04 |
| 7844446 | Method and system for multiprocessor emulation on a multiprocessor host system | Ravi Nair, John Kevin Patrick O'Brien, Kathryn M. O'Brien, Peter Howland Oden, Daniel A. Prener +1 more | 2010-11-30 |
| 7735072 | Method and apparatus for profiling computer program execution | Kemal Ebcioglu, Michael K. Gschwind, Sumedh W. Sathaye | 2010-06-08 |
| 7516310 | Method to reduce the number of times in-flight loads are searched by store instructions in a multi-threaded processor | Vijayalakshmi Srinivasan | 2009-04-07 |
| 7509457 | Non-homogeneous multi-processor system with shared memory | Peter G. Capek, Michael K. Gschwind, Charles Ray Johns, Harm Peter Hofstee, Martin E. Hopkins +4 more | 2009-03-24 |
| 7496494 | Method and system for multiprocessor emulation on a multiprocessor host system | Ravi Nair, John Kevin Patrick O'Brien, Kathryn M. O'Brien, Peter Howland Oden, Daniel A. Prener +1 more | 2009-02-24 |
| 7496733 | System and method of execution of register pointer instructions ahead of instruction issues | Michael K. Gschwind, Jude A. Rivers, Sumedh W. Sathaye, John-David Wellman, Victor Zyuban | 2009-02-24 |
| 7487330 | Method and apparatus for transferring control in a computer system with dynamic compilation capability | Kemal Ebcioglu, Michael K. Gschwind, David Arnold Luick | 2009-02-03 |
| 7461209 | Transient cache storage with discard function for disposable data | Michael K. Gschwind, Robert K. Montoye, Jude A. Rivers, Sumedh W. Sathaye, John-David Wellman +1 more | 2008-12-02 |
| 7401209 | Limiting entries searched in load reorder queue to between two pointers for match with executing load instruction | Vijayalakshmi Srinivasan | 2008-07-15 |
| 7356673 | System and method including distributed instruction buffers for storing frequently executed instructions in predecoded form | Clair John Glossner, III, Erdem Hokenek, David Meltzer, Mayan Moudgill | 2008-04-08 |
| 7340588 | Extending the number of instruction bits in processors with fixed length instructions, in a manner compatible with existing code | Michael K. Gschwind, David Arnold Luick, Daniel A. Prener, Jude A. Rivers, Sumedh W. Sathaye +1 more | 2008-03-04 |
| 7325124 | System and method of execution of register pointer instructions ahead of instruction issue | Michael K. Gschwind, Jude A. Rivers, Sumedh W. Sathaye, John-David Wellman, Victor Zyuban | 2008-01-29 |