DT

Douglas M. Trickett

IBM: 12 patents #9,222 of 70,183Top 15%
Globalfoundries: 8 patents #444 of 4,424Top 15%
TL Tokyo Electron Limited: 7 patents #1,084 of 5,567Top 20%
SS Stmicroelectronics Sa: 4 patents #351 of 1,676Top 25%
HH Hitachi High-Technologies: 1 patents #1,282 of 1,917Top 70%
Overall (All Time): #272,307 of 4,157,543Top 7%
17
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
10957588 Chamferless via structures Mark L. Lenhardt, Frank W. Mont, Brown C. Peethala, Shariq Siddiqui, Jessica P. Striss 2021-03-23
10937694 Chamferless via structures Mark L. Lenhardt, Frank W. Mont, Brown C. Peethala, Shariq Siddiqui, Jessica P. Striss 2021-03-02
10903118 Chamferless via structures Mark L. Lenhardt, Frank W. Mont, Brown C. Peethala, Shariq Siddiqui, Jessica P. Striss 2021-01-26
10388565 Chamferless via structures Mark L. Lenhardt, Frank W. Mont, Brown C. Peethala, Shariq Siddiqui, Jessica P. Striss 2019-08-20
10032668 Chamferless via structures Mark L. Lenhardt, Frank W. Mont, Brown C. Peethala, Shariq Siddiqui, Jessica P. Striss 2018-07-24
9799559 Methods employing sacrificial barrier layer for protection of vias during trench formation Shariq Siddiqui, Frank W. Mont, Xunyuan Zhang, Brown C. Peethala 2017-10-24
9768113 Self aligned via in integrated circuit Yannick Feurprier, Joe Lee, Lars Liebmann, Yann Mignot, Terry A. Spooner +1 more 2017-09-19
9613862 Chamferless via structures Mark L. Lenhardt, Frank W. Mont, Brown C. Peethala, Shariq Siddiqui, Jessica P. Striss 2017-04-04
9385078 Self aligned via in integrated circuit Yannick Feurprier, Joe Lee, Lars Liebmann, Yann Mignot, Terry A. Spooner +1 more 2016-07-05
9373543 Forming interconnect features with reduced sidewall tapering Frank W. Mont, Shariq Siddiqui, Brown C. Peethala 2016-06-21
9373582 Self aligned via in integrated circuit Yannick Feurprier, Joe Lee, Lars Liebmann, Yann Mignot, Terry A. Spooner +1 more 2016-06-21
9252051 Method for top oxide rounding with protection of patterned features Joe Lee, Yann Mignot 2016-02-02
8476165 Method for thinning a bonding wafer Atsushi Yamashita 2013-07-02
8202803 Method to remove capping layer of insulation dielectric in interconnect structures Yannick Feurprier 2012-06-19
7772110 Electrical contacts for integrated circuits and methods of forming using gas cluster ion beam processing Rodney L. Robison 2010-08-10
7279427 Damage-free ashing process and system for post low-k etch Masaru Nishino 2007-10-09
6875477 Method for coating internal surface of plasma processing chamber Muneo Furuse 2005-04-05