Issued Patents All Time
Showing 25 most recent of 369 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12119393 | Punch through stopper in bulk finFET device | Veeraraghavan S. Basker, Zuoguang Liu, Tenko Yamashita | 2024-10-15 |
| 11869893 | Stacked field effect transistor with wrap-around contacts | Ruilong Xie, Alexander Reznicek, Dechao Guo | 2024-01-09 |
| 11862710 | Vertical transistor including symmetrical source/drain extension junctions | Alexander Reznicek, Veeraraghavan S. Basker, Junli Wang | 2024-01-02 |
| 11688646 | Reduced source/drain coupling for CFET | Ruilong Xie, Alexander Reznicek, Chanro Park | 2023-06-27 |
| 11610101 | Formation failure resilient neuromorphic device | Youngseok Kim, Jungwook Choi, Seyoung Kim | 2023-03-21 |
| 11575025 | Vertical field effect transistor with self-aligned source and drain top junction | Ruilong Xie, Alexander Reznicek, Chen Zhang | 2023-02-07 |
| 11562906 | Low resistance source drain contact formation with trench metastable alloys and laser annealing | Oleg Gluschenkov, Zuoguang Liu, Shogo Mochizuki, Hiroaki Niimi, Tenko Yamashita | 2023-01-24 |
| 11502202 | Transistors with uniform source/drain epitaxy | Kangguo Cheng, Ruilong Xie, Tenko Yamashita | 2022-11-15 |
| 11494655 | Random matrix hardware for machine learning | Xiao Sun, Youngseok Kim | 2022-11-08 |
| 11404560 | Punch through stopper in bulk finFET device | Veeraraghavan S. Basker, Zuoguang Liu, Tenko Yamashita | 2022-08-02 |
| 11374111 | Forming replacement low-k spacer in tight pitch fin field effect transistors | Xiuyu Cai, Qing Liu, Ruilong Xie | 2022-06-28 |
| 11355633 | Vertical field effect transistor with bottom source-drain region | Alexander Reznicek, Ruilong Xie, Balasubramanian S. Pranatharthi Haran | 2022-06-07 |
| 11348999 | Nanosheet semiconductor devices with sigma shaped inner spacer | Alexander Reznicek, Veeraraghavan S. Basker, Junli Wang | 2022-05-31 |
| 11335804 | Scalable vertical transistor bottom source-drain epitaxy | Ruilong Xie, Alexander Reznicek | 2022-05-17 |
| 11309408 | Aspect ratio trapping in channel last process | Effendi Leobandung | 2022-04-19 |
| 11239343 | Vertical transistor including symmetrical source/drain extension junctions | Alexander Reznicek, Veeraraghavan S. Basker, Junli Wang | 2022-02-01 |
| 11239342 | Vertical transistors having improved control of top source or drain junctions | Kangguo Cheng, Ruilong Xie, Tenko Yamashita | 2022-02-01 |
| 11201153 | Stacked field effect transistor with wrap-around contacts | Ruilong Xie, Alexander Reznicek, Dechao Guo | 2021-12-14 |
| 11183558 | Nanosheet transistor having partially self-limiting bottom isolation extending into the substrate and under the source/drain and gate regions | Veeraraghavan S. Basker, Alexander Reznicek, Junli Wang | 2021-11-23 |
| 11177370 | Vertical field effect transistor with self-aligned source and drain top junction | Ruilong Xie, Alexander Reznicek, Chen Zhang | 2021-11-16 |
| 11171204 | High thermal budget compatible punch through stop integration using doped glass | Kangguo Cheng, Sanjay C. Mehta, Xin Miao | 2021-11-09 |
| 11164787 | Two-stage top source drain epitaxy formation for vertical field effect transistors enabling gate last formation | Alexander Reznicek, Zuoguang Liu, Ruilong Xie | 2021-11-02 |
| 11164793 | Reduced source/drain coupling for CFET | Ruilong Xie, Alexander Reznicek, Chanro Park | 2021-11-02 |
| 11158636 | Nanosheet device integrated with a FINFET transistor | Ruilong Xie, Alexander Reznicek | 2021-10-26 |
| 11152460 | High thermal budget compatible punch through stop integration using doped glass | Kangguo Cheng, Sanjay C. Mehta, Xin Miao | 2021-10-19 |