Issued Patents All Time
Showing 25 most recent of 42 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12405904 | Sharing memory and I/O services between nodes | Debendra Das Sharma, Robert G. Blankenship, Suresh Chittor, Kenneth C. Creta, Balint Fleischer +2 more | 2025-09-02 |
| 12407764 | Securely exposing an accelerator to privileged system components | Joshua David Fender, Utkarsh Y. Kakaiya, Mohan Nair, Pratik M. Marolia | 2025-09-02 |
| 12399832 | Shared buffered memory routing | Debendra Das Sharma, Michelle C. Jen | 2025-08-26 |
| 12252891 | Deck fasteners alignment tool | — | 2025-03-18 |
| 12254061 | Apparatuses and methods to accelerate matrix multiplication | Maciej Urbanski, Brian J. Hickmann, Michael Rotzin, Krishnakumar Narayanan Nair, Andrew Yang +1 more | 2025-03-18 |
| 12205035 | Artificial neural network training using flexible floating point tensors | Krishnakumar Narayanan Nair, Andrew Yang | 2025-01-21 |
| 11755486 | Shared buffered memory routing | Debendra Das Sharma, Michelle C. Jen | 2023-09-12 |
| 11227383 | System and method for automated cosmetic inspection of electronic devices | Clark Humphrey | 2022-01-18 |
| 11113196 | Shared buffered memory routing | Debendra Das Sharma, Michelle C. Jen | 2021-09-07 |
| 10915468 | Sharing memory and I/O services between nodes | Debendra Das Sharma, Robert G. Blankenship, Suresh Chittor, Kenneth C. Creta, Balint Fleischer +2 more | 2021-02-09 |
| 10762244 | Securely exposing an accelerator to privileged system components | Joshua David Fender, Utkarsh Y. Kakaiya, Mohan Nair, Pratik M. Marolia | 2020-09-01 |
| 10671740 | Supporting configurable security levels for memory address ranges | Binata Bhattacharyya, Raghunandan Makaram, Amy L. Santoni, George Z. Chrysos, Simon P. Johnson +1 more | 2020-06-02 |
| 10579464 | Method and apparatus for partial cache line sparing | Debaleena Das, Rajat Agarwal | 2020-03-03 |
| 10402964 | System and method for automated cosmetic inspection of electronic devices | Clark Humphrey | 2019-09-03 |
| 10360096 | Error handling in transactional buffered memory | Bill Nale, Robert G. Blankenship, Eric L. Hendrickson | 2019-07-23 |
| 10198379 | Early identification in transactional buffered memory | Bill Nale, Robert G. Blankenship, Jeffrey C. Swanson | 2019-02-05 |
| 10184882 | System and method for providing user guidance for electronic device processing | Clark Humphrey, Joel McCarty | 2019-01-22 |
| 10169858 | System and method for automated cosmetic inspection of electronic devices | Clark Humphrey | 2019-01-01 |
| 10163508 | Supporting multiple memory types in a memory slot | Woojong Han, Mohamed Arafa, Mani N. Prakash, James K. Pickett, John K. Grooms +3 more | 2018-12-25 |
| 10102886 | Techniques for probabilistic dynamic random access memory row repair | John H. Crawford, Sreenivas Mandava, Raj K. Ramanujan | 2018-10-16 |
| 10061719 | Packed write completions | Jeffrey C. Swanson, Bill Nale, Robert G. Blankenship, Jeff Willey, Eric L. Hendrickson | 2018-08-28 |
| 10042562 | Apparatus and method for a non-power-of-2 size cache in a first level memory device to cache data present in a second level memory device | Vedaraman Geetha, Henk G. Neefs, Sreenivas Mandava, Massimo Sutera | 2018-08-07 |
| 10031861 | Protect non-memory encryption engine (non-mee) metadata in trusted execution environment | Siddhartha Chhabra, Binata Bhattacharyya, Raghunandan Makaram | 2018-07-24 |
| 10007606 | Implementation of reserved cache slots in computing system having inclusive/non inclusive tracking and two level system memory | Vedaraman Geetha, Binata Bhattacharyya, Massimo Sutera | 2018-06-26 |
| 9959418 | Supporting configurable security levels for memory address ranges | Binata Bhattacharyya, Raghunandan Makaram, Amy L. Santoni, George Z. Chrysos, Simon P. Johnson +1 more | 2018-05-01 |