Issued Patents All Time
Showing 25 most recent of 28 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12229557 | Atomic operation predictor to predict whether an atomic operation will complete successfully | Gideon N. Levinsky, Michael L. Karm | 2025-02-18 |
| 12079140 | Reducing translation lookaside buffer searches for splintered pages | John D. Pape, Peter G. Soderquist | 2024-09-03 |
| 11928467 | Atomic operation predictor to predict whether an atomic operation will complete successfully | Gideon N. Levinsky, Michael L. Karm | 2024-03-12 |
| 11720501 | Cache replacement based on traversal tracking | Peter G. Soderquist | 2023-08-08 |
| 11675710 | Limiting translation lookaside buffer searches using active page size | John D. Pape, Peter G. Soderquist | 2023-06-13 |
| 11615033 | Reducing translation lookaside buffer searches for splintered pages | John D. Pape, Peter G. Soderquist | 2023-03-28 |
| 11429535 | Cache replacement based on traversal tracking | Peter G. Soderquist | 2022-08-30 |
| 11422946 | Translation lookaside buffer striping for efficient invalidation operations | John D. Pape, Peter G. Soderquist | 2022-08-23 |
| 11347514 | Content-addressable memory filtering based on microarchitectural state | Deepak Limaye, Gideon N. Levinsky | 2022-05-31 |
| 11119767 | Atomic operation predictor to predict if an atomic operation will successfully complete and a store queue to selectively forward data based on the predictor | Gideon N. Levinsky, Michael L. Karm | 2021-09-14 |
| 11099990 | Managing serial miss requests for load operations in a non-coherent memory system | Gideon N. Levinsky, Deepak Limaye, Mridul Agarwal | 2021-08-24 |
| 10909035 | Processing memory accesses while supporting a zero size cache in a cache hierarchy | — | 2021-02-02 |
| 10725928 | Translation lookaside buffer invalidation by range | Pradeep Kanapathipillai, Joshua William Smith | 2020-07-28 |
| 9772851 | Retrieving instructions of a single branch, backwards short loop from a local loop buffer or virtual loop buffer | Ronald P. Hall, Michael L. Karm, David Mui | 2017-09-26 |
| 9632788 | Buffering instructions of a single branch, backwards short loop within a virtual loop buffer | Ronald P. Hall, Michael L. Karm, David Mui | 2017-04-25 |
| 9489204 | Method and apparatus for precalculating a direct branch partial target address during a misprediction correction process | Jiajin Tu, Suresh K. Venkumahanti | 2016-11-08 |
| 9489207 | Processor and method for partially flushing a dispatched instruction group including a mispredicted branch | William E. Burky, Dung Q. Nguyen, Balaram Sinharoy, Benjamin W. Stolt | 2016-11-08 |
| 9395995 | Retrieving instructions of a single branch, backwards short loop from a virtual loop buffer | Ronald P. Hall, Michael L. Karm, David Mui | 2016-07-19 |
| 9342432 | Hardware performance-monitoring facility usage after context swaps | Giles R. Frazier | 2016-05-17 |
| 9189365 | Hardware-assisted program trace collection with selectable call-signature capture | Giles R. Frazier, David S. Levitan, Mauricio J. Serrano | 2015-11-17 |
| 9069563 | Reducing store-hit-loads in an out-of-order processor | Brian R. Konigsburg, David S. Levitan, David Mui | 2015-06-30 |
| 9052910 | Efficiency of short loop instruction fetch | Ronald P. Hall, Michael L. Karm, David Mui | 2015-06-09 |
| 8898667 | Dynamically manage applications on a processing system | Lydia M. Do, Jason A. Cox, Kimberly M. Fernsler, Michael L. Karm | 2014-11-25 |
| 8868886 | Task switch immunized performance monitoring | Giles R. Frazier, David S. Levitan | 2014-10-21 |
| 8489866 | Branch trace history compression | Mauricio J. Serrano | 2013-07-16 |