Issued Patents All Time
Showing 25 most recent of 76 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12182576 | Executing a composite scalar-vector VLIW instruction having a repeat field | Thomas W. Fox, Arpith Chacko Jacob, Hans M. Jacobson, Ravi Nair, Kevin O'Brien +1 more | 2024-12-31 |
| 11860702 | Current consumption controller | Xin Zhang, Leland Chang | 2024-01-02 |
| 11775257 | Enhanced low precision binary floating-point formatting | Silvia M. Mueller, Ankur Agrawal, Kailash Gopalakrishnan, Dongsoo Lee | 2023-10-03 |
| 11669489 | Sparse systolic array design | Swagath Venkataramani, Sanchari Sen, Vijayalakshmi Srinivasan, Ankur Agrawal, Sunil K. Shukla +1 more | 2023-06-06 |
| 11620132 | Reusing an operand received from a first-in-first-out (FIFO) buffer according to an operand specifier value specified in a predefined field of an instruction | Sunil K. Shukla, Vijayalakshmi Srinivasan, Jungwook Choi | 2023-04-04 |
| 11455142 | Ultra-low precision floating-point fused multiply-accumulate unit | Ankur Agrawal, Silvia M. Mueller, Kailash Gopalakrishnan, Balaram Sinharoy, Mingu Kang | 2022-09-27 |
| 11347517 | Reduced precision based programmable and SIMD dataflow architecture | Kailash Gopalakrishnan, Sunil K. Shukla, Jungwook Choi, Silvia M. Mueller, Vijayalakshmi Srinivasan +2 more | 2022-05-31 |
| 11314482 | Low latency floating-point division operations | Silvia M. Mueller, Thomas W. Fox | 2022-04-26 |
| 11281745 | Half-precision floating-point arrays at low overhead | Jose E. Moreira, Joel A. Silberman | 2022-03-22 |
| 11223703 | Instruction initialization in a dataflow architecture | Brian W. Curran, Kailash Gopalakrishnan, Sunil K. Shukla | 2022-01-11 |
| 11216281 | Facilitating data processing using SIMD reduction operations across SIMD lanes | Kailash Gopalakrishnan, Jinwook Oh, Sunil K. Shukla, Silvia M. Mueller | 2022-01-04 |
| 11182127 | Binary floating-point multiply and scale operation for compute-intensive numerical applications and apparatuses | Silvia M. Mueller, Ankur Agrawal, Kailash Gopalakrishnan | 2021-11-23 |
| 11157280 | Dynamic fusion based on operand size | Maarten J. Boersma, Robert Alan Philhower, Balaram Sinharoy | 2021-10-26 |
| 11138010 | Loop management in multi-processor dataflow architecture | Chia-Yu Chen, Jungwook Choi, Brian W. Curran, Kailash Gopalakrishnan, Jinwook Oh +2 more | 2021-10-05 |
| 11095313 | Employing single error correction and triple error detection to optimize bandwidth and resilience under multiple bit failures | Robert K. Montoye, Jeffrey H. Derby, Prashant Jayaprakash Nair | 2021-08-17 |
| 10838868 | Programmable data delivery by load and store agents on a processing chip interfacing with on-chip memory components and directing data to external memory components | Chia-Yu Chen, Jungwook Choi, Brian W. Curran, Kailash Gopalakrishan, Jinwook Oh +3 more | 2020-11-17 |
| 10656913 | Enhanced low precision binary floating-point formatting | Silvia M. Mueller, Ankur Agrawal, Kailash Gopalakrishnan, Dongsoo Lee | 2020-05-19 |
| 10572263 | Executing a composite VLIW instruction having a scalar atom that indicates an iteration of execution | Thomas W. Fox, Arpith Chacko Jacob, Hans M. Jacobson, Ravi Nair, Kevin O'Brien +1 more | 2020-02-25 |
| 10565285 | Processor and memory transparent convolutional lowering and auto zero padding for deep neural network implementations | Jungwook Choi, Vijayalakshmi Srinivasan, Swagath Venkataramani | 2020-02-18 |
| 10275256 | Branch prediction in a computer processor | Michael N. Goulet, David S. Levitan, Nicholas R. Orzol | 2019-04-30 |
| 10162634 | Extendable conditional permute SIMD instructions | Alexander E. Eichenberger | 2018-12-25 |
| 10049061 | Active memory device gather, scatter, and filter | Thomas W. Fox, Hans M. Jacobson, James Allan Kahle, Jaime Moreno, Ravi Nair | 2018-08-14 |
| 9971713 | Multi-petascale highly efficient parallel supercomputer | Sameh W. Asaad, Ralph E. Bellofatto, Michael A. Blocksome, Matthias A. Blumrich, Peter Boyle +54 more | 2018-05-15 |
| 9928190 | High bandwidth low latency data exchange between processing elements | Thomas W. Fox, Hans M. Jacobson, Ravi Nair | 2018-03-27 |
| 9910802 | High bandwidth low latency data exchange between processing elements | Thomas W. Fox, Hans M. Jacobson, Ravi Nair | 2018-03-06 |