Issued Patents All Time
Showing 76–100 of 148 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11221762 | Common platform for one-level memory architecture and two-level memory architecture | Joydeep Ray, Inder M. Sodhi, Jeffrey R. Wilcox | 2022-01-11 |
| 11204977 | Scalable sparse matrix multiply acceleration using systolic arrays with feedback inputs | Subramaniam Maiyuran, Jorge Parra, Supratim Pal, Ashutosh Garg, Shubra Marwaha +3 more | 2021-12-21 |
| 11151769 | Graphics architecture including a neural network pipeline | Hugues Labbe, DARREL PALKE, Sherine Abdelhak, Jill MacDonald Boyce, Scott Janus +10 more | 2021-10-19 |
| 11119820 | Local memory sharing between kernels | Valentin Andrei, Aravindh Anantaraman, Abhishek R. Appu, Nicolas C. Galoppo Von Borries, Altug Koker +6 more | 2021-09-14 |
| 11113784 | Sparse optimizations for a matrix accelerator architecture | Joydeep Ray, Scott Janus, Subramaniam Maiyuran, Altug Koker, Abhishek R. Appu +12 more | 2021-09-07 |
| 11042370 | Instruction and logic for systolic dot product with accumulate | Subramaniam Maiyuran, Guei-Yuan Lueh, Supratim Pal, Ashutosh Garg, Chandra Gurram +10 more | 2021-06-22 |
| 11036545 | Graphics systems and methods for accelerating synchronization using fine grain dependency check and scheduling optimizations based on available shared memory space | Subramaniam Maiyuran, Altug Koker, Aravindh Anantaraman, SungYe Kim, Valentin Andrei +1 more | 2021-06-15 |
| 11016929 | Scalar core integration | Joydeep Ray, Aravindh Anantaraman, Abhishek R. Appu, Altug Koker, Elmoustapha Ould-Ahmed-Vall +10 more | 2021-05-25 |
| 10970808 | Shared local memory read merge and multicast return | Joydeep Ray, Subramaniam Maiyuran, Vivek Kumar Ilanchelian | 2021-04-06 |
| 10909652 | Enabling product SKUs based on chiplet configurations | Altug Koker, Lance Cheney, Eric Finley, Sanjeev Jahagirdar, Josh B. Mastronarde +6 more | 2021-02-02 |
| 10861225 | Neural network processing for multi-object 3D modeling | Jill MacDonald Boyce, Soethiha Soe, Selvakumar Panneer, Adam T. Lake, Nilesh Jain +7 more | 2020-12-08 |
| 10803548 | Disaggregation of SOC architecture | Naveen Matam, Lance Cheney, Eric Finley, Sanjeev Jahagirdar, Altug Koker +6 more | 2020-10-13 |
| 10761898 | Migrating threads between asymmetric cores in a multiple core processor | Sanjeev Jahagirdar, Inder M. Sodhi | 2020-09-01 |
| 10740281 | Asymmetric performance multicore architecture with same instruction set architecture | Sanjeev Jahagirdar, Deborah T. Marr | 2020-08-11 |
| 10228861 | Common platform for one-level memory architecture and two-level memory architecture | Joydeep Ray, Inder M. Sodhi, Jeffrey R. Wilcox | 2019-03-12 |
| 10049080 | Asymmetric performance multicore architecture with same instruction set architecture | Sanjeev Jahagirdar, Deborah T. Marr | 2018-08-14 |
| 9984038 | Method, apparatus, and system for optimizing frequency and performance in a multidie microprocessor | Jose P. Allarey, Sanjeev Jahagirdar, Oren Lamdan | 2018-05-29 |
| 9952281 | Clock jitter and power supply noise analysis | Rubil Ahmadi, Jesse Max Guss | 2018-04-24 |
| 9874925 | Method and apparatus for a zero voltage processor sleep state | Sanjeev Jahagirdar, John B. Conrad, Robert Milstrey, Stephen A. Fischer, Alon Naveh +1 more | 2018-01-23 |
| 9870044 | Method and apparatus for a zero voltage processor sleep state | Sanjeev Jahagirdar, John B. Conrad, Robert Milstrey, Stephen A. Fischer, Alon Naveh +1 more | 2018-01-16 |
| 9841807 | Method and apparatus for a zero voltage processor sleep state | Sanjeev Jahagirdar, John B. Conrad, Robert Milstrey, Stephen A. Fischer, Alon Naveh +1 more | 2017-12-12 |
| 9727388 | Migrating threads between asymmetric cores in a multiple core processor | Sanjeev Jahagirdar, Inder M. Sodhi | 2017-08-08 |
| 9690353 | System and method for initiating a reduced power mode for one or more functional blocks of a processor based on various types of mode request | Douglas R. Moran, Achmed R. Zahir, William Knolla, Hartej Singh, Vasudev Bibikar +3 more | 2017-06-27 |
| 9626316 | Managing shared resources between multiple processing devices | Inder M. Sodhi, Joydeep Ray | 2017-04-18 |
| 9600413 | Common platform for one-level memory architecture and two-level memory architecture | Joydeep Ray, Inder M. Sodhi, Jeffrey R. Wilcox | 2017-03-21 |