Issued Patents All Time
Showing 51–75 of 86 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7017026 | Generating lookahead tracked register value based on arithmetic operation indication | Adi Yoaz, Stephan Jourdan, Michael Bekerman | 2006-03-21 |
| 6950903 | Power reduction for processor front-end by caching decoded instructions | Baruch Solomon, Doron Orenstien | 2005-09-27 |
| 6950928 | Apparatus, method and system for fast register renaming using virtual renaming, including by using rename information or a renamed register | Adi Yoaz, Gregory Pribush | 2005-09-27 |
| 6910121 | System and method of reducing the number of copies from alias registers to real registers in the commitment of instructions | Guillermo Savransky | 2005-06-21 |
| 6880063 | Memory cache bank prediction | Adi Yoaz, Lihu Rappoport, Mattan Erez, Stephan Jourdan, Bob Valentine | 2005-04-12 |
| 6857060 | System, apparatus and method for prioritizing instructions and eliminating useless instructions | George Elias, Adi Yoaz | 2005-02-15 |
| 6804632 | Distribution of processing activity across processing hardware based on power consumption considerations | Doron Orenstien | 2004-10-12 |
| 6772317 | Method and apparatus for optimizing load memory accesses | Stephan Jourdan, Michael Bekerman | 2004-08-03 |
| 6757816 | Fast branch misprediction recovery method and system | Adi Yoaz, Gregory Pribush, Freddy Gabby, Mattan Erez | 2004-06-29 |
| 6742112 | Lookahead register value tracking | Adi Yoaz, Stephan Jourdan, Michael Bekerman | 2004-05-25 |
| 6697933 | Method and apparatus for fast, speculative floating point register renaming | Gregory Pribush, Bishara Shomar | 2004-02-24 |
| 6697932 | System and method for early resolution of low confidence branches and safe data cache accesses | Adi Yoaz, Mattan Erez | 2004-02-24 |
| 6694421 | Cache memory bank access prediction | Adi Yoaz, Lihu Rappoport, Mattan Erez, Stephan Jourdan, Bob Valentine | 2004-02-17 |
| 6687838 | Low-power processor hint, such as from a PAUSE instruction | Doron Orenstien | 2004-02-03 |
| 6678808 | Memory record update filtering | Stephan Jourdan, Michael Bekerman | 2004-01-13 |
| 6678816 | Method for optimized representation of page table entries | Andrew F. Glew, Maury J. Bach, Robert Valentine, Richard Uhlig, Opher Kahn | 2004-01-13 |
| 6675376 | System and method for fusing instructions | Alexander Peleg, Nathaniel Hoffman | 2004-01-06 |
| 6647482 | Method for optimized representation of page table entries | Andrew F. Glew, Maury J. Bach, Robert Valentine, Richard Uhlig, Opher Kahn | 2003-11-11 |
| 6631445 | Cache structure for storing variable length data | Lihu Rappoport, Stephan Jourdan | 2003-10-07 |
| 6625723 | Unified renaming scheme for load and store instructions | Stephen J. Jourday, Adi Yoaz, Michael Bekerman | 2003-09-23 |
| 6625744 | Controlling population size of confidence assignments | Lihu Rappoport | 2003-09-23 |
| 6601155 | Hot way caches: an energy saving technique for high performance caches | Evgeni Krimer, Bishara Shomar | 2003-07-29 |
| 6601161 | Method and system for branch target prediction using path information | Lihu Rappoport, Nicolas Kacevas, Oded Lempel | 2003-07-29 |
| 6594754 | Mapping destination logical register to physical register storing immediate or renamed source register of move instruction and using mapping counters | Stephan Jourdan, Gad Sheaffer | 2003-07-15 |
| 6553469 | Memory record update filtering | Stephan Jourdan, Michael Bekerman | 2003-04-22 |