Issued Patents All Time
Showing 101–125 of 196 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10019354 | Apparatus and method for fast cache flushing including determining whether data is to be stored in nonvolatile memory | Sarathy Jayakumar, Eswaramoorthi Nallusamy | 2018-07-10 |
| 10007528 | Computing platform interface with memory management | Guy M. Therien, Paul S. Diefenbaugh, Anil Aggarwal, Andrew D. Henroid, Jeremy J. Shrall +9 more | 2018-06-26 |
| 9977618 | Pooling of memory resources across multiple nodes | Debendra Das Sharma, Balint Fleischer | 2018-05-22 |
| 9921997 | Mechanism for PCIE cable topology discovery in a rack scale architecture environment | Murugasamy K. Nachimuthu | 2018-03-20 |
| 9904586 | Interfacing with block-based storage in a processor | Theodros Yigzaw, Hisham Shafi, Ron Gabor, Ashok Raj | 2018-02-27 |
| 9864603 | Instruction and logic for machine check interrupt management | Ashok Raj | 2018-01-09 |
| 9842015 | Instruction and logic for machine checking communication | Ashok Raj, Jose A. Vargas, William G. Auld, Cameron McNairy, Theodros Yigzaw +2 more | 2017-12-12 |
| 9829951 | Enhanced system sleep state support in servers using non-volatile random access memory | Murugasamy K. Nachimuthu | 2017-11-28 |
| 9823849 | Method and apparatus for dynamically allocating storage resources to compute nodes | Mark A. Schmisseur, Balint Fleischer, Debendra Das Sharma, Raj K. Ramanujan | 2017-11-21 |
| 9792190 | High performance persistent memory | Murugasamy K. Nachimuthu, George Vergis | 2017-10-17 |
| 9779094 | Systems and methods for tagging emails by discussions | Gary Lehrman, Hari Krishna Dara | 2017-10-03 |
| 9753793 | Techniques for handling errors in persistent memory | Murugasamy K. Nachimuthu, Camille C. Raad | 2017-09-05 |
| 9686143 | Mechanism for management controllers to learn the control plane hierarchy in a data center environment | Ramamurthy Krithivas, Narayan Ranganathan, John Chun Kwok Leung | 2017-06-20 |
| 9645829 | Techniques to communicate with a controller for a non-volatile dual in-line memory module | Sarathy Jayakumar, Adam J. Brooks, George Vergis | 2017-05-09 |
| 9612887 | Firmware-related event notification | Sarathy Jayakumar, Vincent J. Zimmer, Rajesh Poornachandran | 2017-04-04 |
| 9612649 | Method and apparatus to shutdown a memory channel | Murugasamy K. Nachimuthu | 2017-04-04 |
| 9600416 | Apparatus and method for implementing a multi-level memory hierarchy | Raj K. Ramanujan, Rajat Agarwal, Kai Cheng, Taarinya Polepeddi, Camille C. Raad +5 more | 2017-03-21 |
| 9594570 | Computing platform with interface based error injection | Sarathy Jayakumar, Jose A. Vargas | 2017-03-14 |
| 9595349 | Hardware apparatuses and methods to check data storage devices for transient faults | Ashok Raj, Ron Gabor, Hisham Shafi, Theodros Yigzaw | 2017-03-14 |
| 9465647 | Providing state storage in a processor for system management mode selectively enabled by register bit instead of external SMRAM | Mahesh S. Natu, Thanunathan Rangarajan, Gautam Doshi, Shamanna M. Datta, Baskaran Ganesan +4 more | 2016-10-11 |
| 9454380 | Computing platform performance management with RAS services | Sarathy Jayakumar, Jose A. Vargas | 2016-09-27 |
| 9448867 | Processor that detects when system management mode attempts to reach program code outside of protected space | Shamanna M. Datta, Rajesh S. Parathasarathy, Mahesh S. Natu, Frank Binns | 2016-09-20 |
| 9448879 | Apparatus and method for implement a multi-level memory hierarchy | Theodros Yigzaw, Oded Lempel, Hisham Shafi, Geeyarpuram N. Santhanakrishnan, Jose A. Vargas +6 more | 2016-09-20 |
| 9430372 | Apparatus, method and system that stores bios in non-volatile random access memory | Murugasamy K. Nachimuthu | 2016-08-30 |
| 9423959 | Method and apparatus for store durability and ordering in a persistent memory architecture | Subramanya R. Dulloor, Sanjay Kumar, Rajesh M. Sankaran, Gilbert Neiger, Richard Uhlig +7 more | 2016-08-23 |