Issued Patents All Time
Showing 26–50 of 76 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8239659 | Vector completion mask handling | Stephan Jourdan, Michael Cornaby, Per Hammarlund, Ronak Signhal, Glenn J. Hinton | 2012-08-07 |
| 7941651 | Method and apparatus for combining micro-operations to process immediate data | Bret L. Toll, John A. Miller | 2011-05-10 |
| 7500049 | Providing a backing store in user-level memory | Martin G. Dixon, Michael Cornaby, Per Hammarlund | 2009-03-03 |
| 7457938 | Staggered execution stack for vector processing | Stephan Jourdan, Avinash Sodani, Per Hammarlund, Ronak Singhal, Glenn J. Hinton | 2008-11-25 |
| 7457932 | Load mechanism | Per Hammarlund, Stephan Jourdan, Glenn J. Hinton, Sebastien Hily, Ronak Singhal | 2008-11-25 |
| 7404065 | Flow optimization and prediction for VSSE memory operations | Stephan Jourdan, Per Hammarlund, Michael Cornaby, Glenn J. Hinton, Avinash Sodani | 2008-07-22 |
| 7103751 | Method and apparatus for representation of an address in canonical form | Bret L. Toll, John A. Miller | 2006-09-05 |
| 6393550 | Method and apparatus for pipeline streamlining where resources are immediate or certainly retired | Glenn J. Hinton, Robert W. Martell, David B. Papworth | 2002-05-21 |
| 6101597 | Method and apparatus for maximum throughput scheduling of dependent operations in a pipelined processor | Robert P. Colwell, Glenn J. Hinton, Robert W. Martell, David B. Papworth | 2000-08-08 |
| 6079014 | Processor that redirects an instruction fetch pipeline immediately upon detection of a mispredicted branch while committing prior instructions to an architectural state | David B. Papworth, Andrew F. Glew, Robert P. Colwell, Glenn J. Hinton | 2000-06-20 |
| 6047369 | Flag renaming and flag masks within register alias table | Robert P. Colwell, Andrew F. Glew, Atiq Bajwa, Glenn J. Hinton | 2000-04-04 |
| 5987600 | Exception handling in a processor that performs speculative out-of-order instruction execution | David B. Papworth, Glenn J. Hinton, Robert P. Colwell, Andrew F. Glew | 1999-11-16 |
| 5974523 | Mechanism for efficiently overlapping multiple operand types in a microprocessor | Andrew F. Glew, Darrell D. Boggs, Glenn J. Hinton, Robert P. Colwell, David B. Papworth | 1999-10-26 |
| 5951670 | Segment register renaming in an out of order processor | Andrew F. Glew | 1999-09-14 |
| 5944817 | Method and apparatus for implementing a set-associative branch target buffer | Bradley D. Hoyt, Glenn Hinton, David B. Papworth, Ashwani K. Gupta, Subramanian Natarajan +2 more | 1999-08-31 |
| 5913050 | Method and apparatus for providing address-size backward compatibility in a processor using segmented memory | Darrell D. Boggs, Robert P. Colwell, Andrew F. Glew, Glenn J. Hinton, David B. Papworth | 1999-06-15 |
| 5903751 | Method and apparatus for implementing a branch target buffer in CISC processor | Bradley D. Hoyt, Glenn J. Hinton, David B. Papworth, Ashwani K. Gupta, Subramanian Natarajan +2 more | 1999-05-11 |
| 5889982 | Method and apparatus for generating event handler vectors based on both operating mode and event type | Scott Dion Rodgers, Rohit A. Vidwans, Joel Huang, Kamla P. Huck | 1999-03-30 |
| 5842036 | Circuit and method for scheduling instructions by predicting future availability of resources required for execution | Glenn J. Hinton, Robert W. Martell, David B. Papworth, James L. Schwartz | 1998-11-24 |
| 5826094 | Register alias table update to indicate architecturally visible state | Robert P. Colwell, David B. Papworth, Andrew F. Glew, Glenn J. Hinton | 1998-10-20 |
| 5812839 | Dual prediction branch system having two step of branch recovery process which activated only when mispredicted branch is the oldest instruction in the out-of-order unit | Bradley D. Hoyt, Glenn J. Hinton, David B. Papworth, Ashwani K. Gupta, Subramanian Natarajan +2 more | 1998-09-22 |
| 5809325 | Circuit and method for scheduling instructions by predicting future availability of resources required for execution | Glenn J. Hinton, Robert W. Martell, David B. Papworth, James L. Schwartz | 1998-09-15 |
| 5809271 | Method and apparatus for changing flow of control in a processor | Robert P. Colwell, Atiq Bajwa, Andrew F. Glew, Glenn J. Hinton, David B. Papworth | 1998-09-15 |
| 5778407 | Methods and apparatus for determining operating characteristics of a memory element based on its physical location | Andrew F. Glew, Glenn J. Hinton, David B. Papworth, Robert P. Colwell, Frederick J. Pollack | 1998-07-07 |
| 5778245 | Method and apparatus for dynamic allocation of multiple buffers in a processor | David B. Papworth, Andrew F. Glew, Glenn J. Hinton, Robert P. Colwell, Shantanu Gupta +1 more | 1998-07-07 |