Issued Patents All Time
Showing 26–50 of 119 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8689154 | Providing timing-closed FinFET designs from planar designs | Mahbub Rashed, David Doman, Yan Wang, Yunfei Deng, Navneet Jain +4 more | 2014-04-01 |
| 8667367 | Memory cell supply voltage control based on error detection | Muhammad M. Khellah, Yibin Ye, Nam Sung Kim, Vivek K. De | 2014-03-04 |
| 8640005 | Method and apparatus for using cache memory in a system that supports a low power state | Christopher B. Wilkerson, Alaa R. Alameldeen, Zeshan A. Chishti, Wei Wu, Shih-Lien Linus Lu | 2014-01-28 |
| 8547777 | Nor logic word line selection | Swaroop Ghosh, Balaji Srinivasan, Fatih Hamzaoglu | 2013-10-01 |
| 8539303 | Low overhead error correcting code protection for stored information | Shih-Lien Linus Lu | 2013-09-17 |
| 8519462 | 6F2 DRAM cell | Yih Wang, M. Clair Webb, Nick Lindert, Swaminathan Sivakumar, Kevin X. Zhang | 2013-08-27 |
| 8488390 | Circuits and methods for memory | Jaydeep P. Kulkarni, James W. Tschanz, Vivek K. De | 2013-07-16 |
| 8456946 | NAND logic word line selection | Swaroop Ghosh, Balaji Srinivasan, Fatih Hamzaoglu | 2013-06-04 |
| 8406073 | Hierarchical DRAM sensing | Gunjan H. Pandya, Kevin X. Zhang, Fatih Hamzaoglu, Balaji Srinivasan, Swaroop Ghosh +1 more | 2013-03-26 |
| 8283771 | Multi-die integrated circuit device and method | Tanay Karnik, Jianping Xu, Yibin Ye | 2012-10-09 |
| 8245111 | Performing multi-bit error correction on a cache line | Zeshan A. Chishti, Alaa R. Alameldeen, Chris Wilkerson, Wei Wu, Muhammad M. Khellah +1 more | 2012-08-14 |
| 8232588 | Increasing the surface area of a memory cell capacitor | Brian S. Doyle, Robert S. Chau, Vivek K. De, Suman Datta | 2012-07-31 |
| 8138042 | Capacitor, method of increasing a capacitance area of same, and system containing same | Brian S. Doyle, Robert S. Chau, Suman Datta, Vivek K. De, Ali Keshavarzi | 2012-03-20 |
| 8030197 | Recessed channel array transistor (RCAT) in replacement metal gate (RMG) logic flow | Brian S. Doyle, Gilbert Dewey, Ravi Pillarisetty, Nick Lindert, Uday Shah | 2011-10-04 |
| 8006164 | Memory cell supply voltage control based on error detection | Khellah Muhammad, Yibin Ye, Nam Sung Kim, Vivek K. De | 2011-08-23 |
| 7999298 | Embedded memory cell and method of manufacturing same | Jack T. Kavalieros, Niloy Mukherjee, Gilbert Dewey, Brian S. Doyle | 2011-08-16 |
| 7981756 | Common plate capacitor array connections, and processes of making same | Nick Lindert, Brian S. Doyle, Christopher J. Jezewski, Swaminathan Sivakumar, Kevin X. Zhang +1 more | 2011-07-19 |
| 7859081 | Capacitor, method of increasing a capacitance area of same, and system containing same | Brian S. Doyle, Robert S. Chau, Suman Datta, Vivek K. De, Ali Keshavarzi | 2010-12-28 |
| 7776684 | Increasing the surface area of a memory cell capacitor | Brian S. Doyle, Robert S. Chau, Vivek K. De, Suman Datta | 2010-08-17 |
| 7767519 | One transistor/one capacitor dynamic random access memory (1T/1C DRAM) cell | Brian S. Doyle, Robert S. Chau | 2010-08-03 |
| 7729445 | Digital outphasing transmitter architecture | Ashoke Ravi, Mostafa Elmala, Richard B. Nicholls, Yorgos Palaskas, Krishnamurthy Soumyanath | 2010-06-01 |
| 7710295 | Inverter based return-to-zero (RZ)+non-RZ (NRZ) signaling | Sourav Saha, Gregory E. Ruhl, Ashoke Ravi | 2010-05-04 |
| 7652910 | Floating body memory array | Uygar E. Avci, Peter L. D. Chang | 2010-01-26 |
| 7653846 | Memory cell bit valve loss detection and restoration | Nam Sung Kim, Muhammad Kheliah, Yibin Ye, Vivek K. De | 2010-01-26 |
| 7602257 | Signal generating circuit | Gerhard Schrom, Fabrice Paillet, Peter Hazucha, Sung T. Moon, Tanay Karnik | 2009-10-13 |