Issued Patents All Time
Showing 26–46 of 46 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10372507 | Compute engine architecture to support data-parallel loops with reduction operations | Ganesh Venkatesh | 2019-08-06 |
| 10289752 | Accelerator for gather-update-scatter operations including a content-addressable memory (CAM) and CAM controller | Ganesh Venkatesh, Nicholas P. Carter | 2019-05-14 |
| 10275247 | Apparatuses and methods to accelerate vector multiplication of vector elements having matching indices | Asit K. Mishra | 2019-04-30 |
| 10198264 | Sorting data and merging sorted data in an instruction set architecture | Asit K. Mishra, Jong Soo Park, Nadathur Rajagopalan Satish, Mikhail Smelyanskiy, Michael Anderson +3 more | 2019-02-05 |
| 10180928 | Heterogeneous hardware accelerator architecture for processing sparse matrix data with skewed non-zero distributions | Eriko Nurvitadhi | 2019-01-15 |
| 10146738 | Hardware accelerator architecture for processing very-sparse and hyper-sparse matrix data | Eriko Nurvitadhi | 2018-12-04 |
| 10049080 | Asymmetric performance multicore architecture with same instruction set architecture | Varghese George, Sanjeev Jahagirdar | 2018-08-14 |
| 9996361 | Byte and nibble sort instructions that produce sorted destination register and destination index mapping | Asit K. Mishra, Kshitij A. Doshi, Elmoustapha Ould-Ahmed-Vall | 2018-06-12 |
| 9594648 | Controlling non-redundant execution in a redundant multithreading (RMT) processor | Glenn J. Hinton, Steven Raasch, Sebastien Hily, John G. Holm, Ronak Singhal +1 more | 2017-03-14 |
| 9569278 | Asymmetric performance multicore architecture with same instruction set architecture | Varghese George, Sanjeev Jahagirdar | 2017-02-14 |
| 9081688 | Obtaining data for redundant multithreading (RMT) execution | Glenn J. Hinton, Steven Raasch, Sebastien Hily, John G. Holm, Ronak Singhal +4 more | 2015-07-14 |
| 8793689 | Redundant multithreading processor | Glenn J. Hinton, Steven Raasch, Avinash Sodani, Sebastien Hily, John G. Holm +1 more | 2014-07-29 |
| 8516024 | Establishing thread priority in a processor or the like | — | 2013-08-20 |
| 8041754 | Establishing thread priority in a processor or the like | — | 2011-10-18 |
| 7451296 | Method and apparatus for pausing execution in a processor or the like | Dion Rodgers | 2008-11-11 |
| 7363474 | Method and apparatus for suspending execution of a thread until a specified memory access occurs | Dion Rodgers, David L. Hill, Shiv Kaushik, James B. Crossland, David A. Koufaty | 2008-04-22 |
| 7143242 | Dynamic priority external transaction system | David L. Hill, Derek T. Bachand, Chinna Prudvi | 2006-11-28 |
| 7127561 | Coherency techniques for suspending execution of a thread until a specified memory access occurs | David L. Hill, Dion Rodgers, Shiv Kaushik, James B. Crossland, David A. Koufaty | 2006-10-24 |
| 6681320 | Causality-based memory ordering in a multiprocessing environment | — | 2004-01-20 |
| 6671795 | Method and apparatus for pausing execution in a processor or the like | Dion Rodgers | 2003-12-30 |
| 6654837 | Dynamic priority external transaction system | David L. Hill, Derek T. Bachand, Chinna Prudvi | 2003-11-25 |