Issued Patents All Time
Showing 1–20 of 20 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11894334 | Dual head capillary design for vertical wire bond | Yuhong Cai, Yi Xu | 2024-02-06 |
| 11848311 | Microelectronic packages having a die stack and a device within the footprint of the die stack | — | 2023-12-19 |
| 11817438 | System in package with interconnected modules | Hyoung Il Kim, Juan E. Dominguez, John G. Meyers | 2023-11-14 |
| 11811182 | Solderless BGA interconnect | Tyler Leuten, Mohammed Rahman | 2023-11-07 |
| 11710674 | Embedded component and methods of making the same | Yi Xu, Dennis Sean Carr | 2023-07-25 |
| 11700696 | Buried electrical debug access port | Florence R. Neumann, Saeed S. Shojaie | 2023-07-11 |
| 11373974 | Electronic device packages and methods for maximizing electrical current to dies and minimizing bond finger size | Mao Guo | 2022-06-28 |
| 11329027 | Microelectronic packages having a die stack and a device within the footprint of the die stack | — | 2022-05-10 |
| 11315843 | Embedded component and methods of making the same | Yi Xu, Dennis Sean Carr | 2022-04-26 |
| 11145632 | High density die package configuration on system boards | Juan E. Dominguez, Hyoung Il Kim, John G. Meyers | 2021-10-12 |
| 11064612 | Buried electrical debug access port | Florence R. Pon, Saeed S. Shojaie | 2021-07-13 |
| 10879152 | Through mold via (TMV) using stacked modular mold rings | Yi Xu | 2020-12-29 |
| 10847450 | Compact wirebonding in stacked-chip system in package, and methods of making same | Saeed S. Shojaie, Hyoung Il Kim, Min-Tih Lai | 2020-11-24 |
| 10490516 | Packaged integrated circuit device with cantilever structure | John G. Meyers, Sireesha Gogineni, Brian J. Long | 2019-11-26 |
| 10475766 | Microelectronics package providing increased memory component density | — | 2019-11-12 |
| 10304814 | I/O layout footprint for multiple 1LM/2LM configurations | Konika Ganguly, Robert J. Royer, Jr., Rebecca Z. Loop, Anthony M. CONSTANTINE | 2019-05-28 |
| 10090261 | Microelectronic package debug access ports and methods of fabricating the same | Florence R. Pon, Saeed S. Shojaie | 2018-10-02 |
| 9972610 | System-in-package logic and method to control an external packaged memory device | — | 2018-05-15 |
| 9871007 | Packaged integrated circuit device with cantilever structure | John G. Meyers, Sireesha Gogineni, Brian J. Long | 2018-01-16 |
| 9646952 | Microelectronic package debug access ports | Florence R. Pon, Saeed S. Shojaie | 2017-05-09 |