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USPTO Patent Rankings Data through Dec 31, 2025
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Bilal Khalaf — 20 Patents

Intel: 20 patents #2,048 of 30,777Top 7%
Folsom, CA: #119 of 1,500 inventorsTop 8%
California: #29,208 of 386,348 inventorsTop 8%
Overall (All Time): #214,803 of 4,157,543Top 6%
20 Patents All Time
Bilal Khalaf has been granted 20 US patents while listed as an inventor at Intel. The first was granted in 2017 and the most recent in February 2024. Bilal Khalaf ranks #214,803 of 4,157,543 US inventors in our database (top 5.2%). Patent records list Bilal Khalaf in Folsom, CA, US.

Issued Patents All Time

Showing 1–20 of 20 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
11894334 Dual head capillary design for vertical wire bond Yuhong Cai, Yi Xu 2024-02-06 $35,892,000
11848311 Microelectronic packages having a die stack and a device within the footprint of the die stack 2023-12-19 $50,836,000
11817438 System in package with interconnected modules Hyoung Il Kim, Juan E. Dominguez, John G. Meyers 2023-11-14
11811182 Solderless BGA interconnect Tyler Leuten, Mohammed Rahman 2023-11-07 $22,371,000
11710674 Embedded component and methods of making the same Yi Xu, Dennis Sean Carr 2023-07-25 $28,608,000
11700696 Buried electrical debug access port Florence R. Neumann, Saeed S. Shojaie 2023-07-11 $21,736,000
11373974 Electronic device packages and methods for maximizing electrical current to dies and minimizing bond finger size Mao Guo 2022-06-28 $15,065,000
11329027 Microelectronic packages having a die stack and a device within the footprint of the die stack 2022-05-10 $19,182,000
11315843 Embedded component and methods of making the same Yi Xu, Dennis Sean Carr 2022-04-26 $25,630,000
11145632 High density die package configuration on system boards Juan E. Dominguez, Hyoung Il Kim, John G. Meyers 2021-10-12 $32,982,000
11064612 Buried electrical debug access port Florence R. Pon, Saeed S. Shojaie 2021-07-13 $34,958,000
10879152 Through mold via (TMV) using stacked modular mold rings Yi Xu 2020-12-29 $24,597,000
10847450 Compact wirebonding in stacked-chip system in package, and methods of making same Saeed S. Shojaie, Hyoung Il Kim, Min-Tih Lai 2020-11-24 $25,522,000
10490516 Packaged integrated circuit device with cantilever structure John G. Meyers, Sireesha Gogineni, Brian J. Long 2019-11-26 $25,149,000
10475766 Microelectronics package providing increased memory component density 2019-11-12 $21,873,000
10304814 I/O layout footprint for multiple 1LM/2LM configurations Konika Ganguly, Robert J. Royer, Jr., Rebecca Z. Loop, Anthony M. CONSTANTINE 2019-05-28 $17,387,000
10090261 Microelectronic package debug access ports and methods of fabricating the same Florence R. Pon, Saeed S. Shojaie 2018-10-02 $23,827,000
9972610 System-in-package logic and method to control an external packaged memory device 2018-05-15 $21,346,000
9871007 Packaged integrated circuit device with cantilever structure John G. Meyers, Sireesha Gogineni, Brian J. Long 2018-01-16 $17,139,000
9646952 Microelectronic package debug access ports Florence R. Pon, Saeed S. Shojaie 2017-05-09 $10,144,000