Issued Patents All Time
Showing 151–173 of 173 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8039888 | Conductive spacers for semiconductor devices and methods of forming | Gary B. Bronner, David M. Fried, Jeffrey P. Gambino, Leland Chang, Ramachandra Divakaruni +2 more | 2011-10-18 |
| 7999319 | Trench-edge-defect-free recrystallization by edge-angle-optimized solid phase epitaxy: method and applications to hybrid orientation substrates | Katherine L. Saenger, Chun-Yung Sung | 2011-08-16 |
| 7999332 | Asymmetric semiconductor devices and method of fabricating | Jun Yuan, Dureseti Chidambarrao, Sunfei Fang, Yue Liang, Xiaojun Yu | 2011-08-16 |
| 7989297 | Asymmetric epitaxy and application thereof | Xinhui Wang, Kevin K. Chan, Zhibin Ren | 2011-08-02 |
| 7977712 | Asymmetric source and drain field effect structure | Huilong Zhu, Hong Lin, Katherine L. Saenger, Kai Xiu | 2011-07-12 |
| 7968915 | Dual stress memorization technique for CMOS application | Thomas S. Kanarsky, Qiqing C. Ouyang | 2011-06-28 |
| 7960263 | Amorphization/templated recrystallization method for hybrid orientation substrates | Keith E. Fogel, Katherine L. Saenger, Chun-Yung Sung | 2011-06-14 |
| 7897468 | Device having self-aligned double gate formed by backside engineering, and device having super-steep retrograded island | Zhijiong Luo, Qingqing Liang, Huilong Zhu | 2011-03-01 |
| 7863712 | Hybrid orientation semiconductor structure with reduced boundary defects and method of forming same | John A. Ott, Katherine L. Saenger, Chun-Yung Sung | 2011-01-04 |
| 7834399 | Dual stress memorization technique for CMOS application | Thomas S. Kanarsky, Qiqing C. Ouyang | 2010-11-16 |
| 7704839 | Buried stress isolation for high-performance CMOS technology | Meikei Ieong, Zhibin Ren | 2010-04-27 |
| 7704852 | Amorphization/templated recrystallization method for hybrid orientation substrates | Keith E. Fogel, Katherine L. Saenger, Chun-Yung Sung | 2010-04-27 |
| 7691733 | Laser processing method for trench-edge-defect-free solid phase epitaxy in confined geometrics | Keith E. Fogel, Kam-Leung Lee, Katherine L. Saenger, Chun-Yung Sung | 2010-04-06 |
| 7682913 | Process for making a MCSFET | Xu Ouyang, Louis L. Hsu, Xinhui Wang | 2010-03-23 |
| 7547616 | Laser processing method for trench-edge-defect-free solid phase epitaxy in confined geometrics | Keith E. Fogel, Kam-Leung Lee, Katherine L. Saenger, Chun-Yung Sung | 2009-06-16 |
| 7541629 | Embedded insulating band for controlling short-channel effect and leakage reduction for DSB process | Huilong Zhu, Zhijiong Luo | 2009-06-02 |
| 7525161 | Strained MOS devices using source/drain epitaxy | Meikei Ieong, Xiao Hu Liu, Qiqing C. Ouyang, Siddhartha Panda | 2009-04-28 |
| 7525162 | Orientation-optimized PFETS in CMOS devices employing dual stress liners | Katherine L. Saenger, Chun-Yung Sung, Kai Xiu | 2009-04-28 |
| 7494886 | Uniaxial strain relaxation of biaxial-strained thin films using ion implantation | Zhibin Ren, Katherine L. Saenger | 2009-02-24 |
| 7465992 | Field effect transistor with mixed-crystal-orientation channel and source/drain regions | Joel P. Desouza, Devendra K. Sadana, Katherine L. Saenger, Chun-Yung Sung, Min Yang | 2008-12-16 |
| 7396407 | Trench-edge-defect-free recrystallization by edge-angle-optimized solid phase epitaxy: method and applications to hybrid orientation substrates | Katherine L. Saenger, Chun-Yung Sung | 2008-07-08 |
| 7384851 | Buried stress isolation for high-performance CMOS technology | Meikei Ieong, Zhibin Ren | 2008-06-10 |
| 7291539 | Amorphization/templated recrystallization method for hybrid orientation substrates | Keith E. Fogel, Katherine L. Saenger, Chun-Yung Sung | 2007-11-06 |