Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11561323 | Intelligent storage device and intelligent storage method | Po-Yuan Hsiao, Chu-An Chung, Wen Tsui, Chi-Chou Chiang | 2023-01-24 |
| 11551289 | Intelligent store system and intelligent store method | Chi-Chou Chiang, Wen Tsui, Yu-Hui Cho | 2023-01-10 |
| 11086881 | Method and device for analyzing data | Hung-Hsuan Chen, Wen Tsui | 2021-08-10 |
| 10984376 | Storage device and storage method to identify object using sensing data and identification model | Wen Tsui, Chu-An Chung, Chun-Chia Lai, Po-Yuan Hsiao | 2021-04-20 |
| 7329563 | Method for fabrication of wafer level package incorporating dual compliant layers | Wei-Chung Lo, Ming Lu | 2008-02-12 |
| 6914333 | Wafer level package incorporating dual compliant layers and method for fabrication | Wei-Chung Lo, Ming Lu | 2005-07-05 |
| 6459150 | Electronic substrate having an aperture position through a substrate, conductive pads, and an insulating layer | Enboa Wu, Tsung-Yao Chu, Rong-Shen Lee | 2002-10-01 |
| 6433427 | Wafer level package incorporating dual stress buffer layers for I/O redistribution and method for fabrication | Enboa Wu, Tsung-Yao Chu, Chung-Tao Chang | 2002-08-13 |
| 6358836 | Wafer level package incorporating elastomeric pads in dummy plugs | Szu-Wei Lu, Kuo-Chuan Chen, Jyh-Rong Lin, Ruoh-Huey Wang, Hsu-Tien Hu | 2002-03-19 |
| 6312974 | Simultaneous bumping/bonding process utilizing edge-type conductive pads and device fabricated | En-Boa Wu, Tsung-Yao Chu | 2001-11-06 |
| 6218726 | Built-in stress pattern on IC dies and method of forming | Chung-Tao Chang, Chia-Chung Wang | 2001-04-17 |
| 6166435 | Flip-chip ball grid array package with a heat slug | Fang-Jun Leu, Rong-Shen Lee, Randy Lo, Chiang-Han Day | 2000-12-26 |