Issued Patents All Time
Showing 126–150 of 165 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7968910 | Complementary field effect transistors having embedded silicon source and drain regions | Thomas W. Dyer, Haining Yang | 2011-06-28 |
| 7960223 | Structure and method to integrate dual silicide with dual stress liner to improve CMOS performance | Haining Yang | 2011-06-14 |
| 7947557 | Heterojunction tunneling field effect transistors, and methods for fabricating the same | Haining Yang | 2011-05-24 |
| 7943454 | Method for dual stress liner | Haining Yang | 2011-05-17 |
| 7935993 | Semiconductor device structure having enhanced performance FET device | Haining Yang | 2011-05-03 |
| 7911008 | SRAM cell having a rectangular combined active area for planar pass gate and planar pull-down NFETS | Shang-Bin Ko, Dae-Gyu Park | 2011-03-22 |
| 7879666 | Semiconductor resistor formed in metal gate stack | Da Zhang, Chendong Zhu, Melanie J. Sherony | 2011-02-01 |
| 7867839 | Method to reduce threshold voltage (Vt) in silicon germanium (SiGe), high-k dielectric-metal gate, p-type metal oxide semiconductor field effect transistors | Jong Ho Lee, Weipeng Li, Dae-Gyu Park, Kenneth J. Stein, Voon-Yew Thean | 2011-01-11 |
| 7863646 | Dual oxide stress liner | Michael P. Belyansky, Thomas W. Dyer, Geng Wang, Haining Yang | 2011-01-04 |
| 7816219 | Field effect transistors (FETs) with multiple and/or staircase silicide | Sunfei Fang, Zhijiong Luo, Haining Yang, Huilong Zhu | 2010-10-19 |
| 7741217 | Dual workfunction silicide diode | Haining Yang | 2010-06-22 |
| 7736966 | CMOS devices with hybrid channel orientations and method for fabricating the same | Thomas W. Dyer, James J. Toomey, Haining Yang | 2010-06-15 |
| 7639170 | System and method for providing operation of internet powered universal remote controller | Wenjie Li, Bin Zhang | 2009-12-29 |
| 7635620 | Semiconductor device structure having enhanced performance FET device | Haining Yang | 2009-12-22 |
| 7612414 | Overlapped stressed liners for improved contacts | Jun Jung Kim, Young-Gun Ko, Jae-Eun Park, Haining Yang | 2009-11-03 |
| 7560312 | Void formation for semiconductor junction capacitance reduction | Haining Yang | 2009-07-14 |
| 7550351 | Structure and method for creation of a transistor | Haining Yang | 2009-06-23 |
| 7531401 | Method for improved fabrication of a semiconductor using a stress proximity technique process | Christopher V. Baiocco, Wenzhi Gao, Young-Gun Ko, Young Way Teh | 2009-05-12 |
| 7521308 | Dual layer stress liner for MOSFETS | Deleep R. Nair, Christopher V. Baiocco, Junjung Kim, Jae-Eun Park, Daewon Yang | 2009-04-21 |
| 7479689 | Electronically programmable fuse having anode and link surrounded by low dielectric constant material | Deok-kee Kim, Haining Yang | 2009-01-20 |
| 7473607 | Method of manufacturing a multi-workfunction gates for a CMOS circuit | Rajesh Rengarajan | 2009-01-06 |
| 7471548 | Structure of static random access memory with stress engineering for stability | Christopher V. Baiocco, Young-Gun Ko, Melanie J. Sherony | 2008-12-30 |
| 7456450 | CMOS devices with hybrid channel orientations and method for fabricating the same | Thomas W. Dyer, James J. Toomey, Haining Yang | 2008-11-25 |
| 7442585 | MOSFET with laterally graded channel region and method for manufacturing same | Huilong Zhu | 2008-10-28 |
| 7432553 | Structure and method to optimize strain in CMOSFETs | Haining Yang | 2008-10-07 |