Issued Patents All Time
Showing 26–41 of 41 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7615433 | Double anneal with improved reliability for dual contact etch stop liner scheme | Khee Yong Lim, Eng Hua Lim, Wenhe Lin, Jamin F. Fen | 2009-11-10 |
| 7482216 | Substrate engineering for optimum CMOS device performance | Meikei Ieong, Min Yang | 2009-01-27 |
| 7473593 | Semiconductor transistors with expanded top portions of gates | Brent A. Anderson, Edward J. Nowak | 2009-01-06 |
| 7462525 | Enhancement of electron and hole mobilities in <110> Si under biaxial compressive strain | Massimo V. Fischetti, John Michael Hergenrother, Meikei Ieong, Rajesh Rengarajan, Alexander Reznicek +3 more | 2008-12-09 |
| 7442611 | Method of applying stresses to PFET and NFET transistor channels for improved performance | Yong Meng Lee, Haining Yang | 2008-10-28 |
| 7436169 | Mechanical stress characterization in semiconductor device | Khee Yong Lim | 2008-10-14 |
| 7396724 | Dual-hybrid liner formation without exposing silicide layer to photoresist stripping chemicals | Haining Yang, Yong Meng Lee, Eng Hua Lim | 2008-07-08 |
| 7314790 | Enhancement of electron and hole mobilities in <110> Si under biaxial compressive strain | Massimo V. Fischetti, John Michael Hergenrother, Meikei Ieong, Rajesh Rengarajan, Alexander Reznicek +3 more | 2008-01-01 |
| 7309637 | Method to enhance device performance with selective stress relief | Yong Meng Lee, Haining Yang | 2007-12-18 |
| 7211869 | Increasing carrier mobility in NFET and PFET transistors on a common wafer | Haining Yang | 2007-05-01 |
| 7193254 | Structure and method of applying stresses to PFET and NFET transistor channels for improved performance | Yong Meng Lee, Haining Yang | 2007-03-20 |
| 7161169 | Enhancement of electron and hole mobilities in <110> Si under biaxial compressive strain | Massimo V. Fischetti, John Michael Hergenrother, Meikei Leong, Rajesh Rengarajan, Alexander Reznicek +3 more | 2007-01-09 |
| 7148559 | Substrate engineering for optimum CMOS device performance | Meikei Leong, Min Yang | 2006-12-12 |
| 7001844 | Material for contact etch layer to enhance device performance | Ashima B. Chakravarti, Shreesh Narasimha, Judson R. Holt, Satya N. Chakravarti | 2006-02-21 |
| 6939814 | Increasing carrier mobility in NFET and PFET transistors on a common wafer | Haining Yang | 2005-09-06 |
| 6821826 | Three dimensional CMOS integrated circuits having device layers built on different crystal oriented wafers | Kathryn Guarini, Meikei Ieong | 2004-11-23 |