Issued Patents All Time
Showing 201–225 of 341 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7233071 | Low-k dielectric layer based upon carbon nanostructures | Toshiharu Furukawa, Mark C. Hakey, David V. Horak, Charles W. Koburger, III | 2007-06-19 |
| 7230681 | Method and apparatus for immersion lithography | Toshiharu Furukawa, Mark C. Hakey, Daniel A. Corliss, David V. Horak, Charles W. Koburger, III | 2007-06-12 |
| 7230335 | Inspection methods and structures for visualizing and/or detecting specific chip structures | Jerome L. Cann, Leendert M. Huisman, Cherie R. Kagan, Leah Pastel, Paul William Pastel +2 more | 2007-06-12 |
| 7229909 | Integrated circuit chip utilizing dielectric layer having oriented cylindrical voids formed from carbon nanotubes | Toshiharu Furukawa, Mark C. Hakey, David V. Horak, Charles W. Koburger, III, Peter H. Mitchell | 2007-06-12 |
| 7229889 | Methods for metal plating of gate conductors and semiconductors formed thereby | Charles W. Koburger, III, David V. Horak, Toshiharu Furukawa, Mark C. Hakey | 2007-06-12 |
| 7227233 | Silicon-on-insulator (SOI) Read Only Memory (ROM) array and method of making a SOI ROM | Toshiharu Furukawa, Mark C. Hakey, David V. Horak, Charles W. Koburger, III, Jack A. Mandelman | 2007-06-05 |
| 7211844 | Vertical field effect transistors incorporating semiconducting nanotubes grown in a spacer-defined passage | Toshiharu Furukawa, Mark C. Hakey, David V. Horak, Peter H. Mitchell, Larry Nesbit | 2007-05-01 |
| 7176089 | Vertical dual gate field effect transistor | Toshiharu Furukawa, Mark C. Hakey, David V. Horak, James M. Leas, William H. Ma +1 more | 2007-02-13 |
| 7129097 | Integrated circuit chip utilizing oriented carbon nanotube conductive layers | Toshiharu Furukawa, Mark C. Hakey, David V. Horak, Charles W. Koburger, III, Peter H. Mitchell | 2006-10-31 |
| 7118997 | Implantation of gate regions in semiconductor device fabrication | Toshiharu Furukawa, Mark C. Hakey, David V. Horak, Charles Koburger | 2006-10-10 |
| 7102201 | Strained semiconductor device structures | Toshiharu Furukawa, Mark C. Hakey, David V. Horak, Charles W. Koburger, III | 2006-09-05 |
| 7087531 | Shallow trench isolation formation | Toshiharu Furukawa, Mark C. Hakey, David V. Horak, Charles W. Koburger, III | 2006-08-08 |
| 7084060 | Forming capping layer over metal wire structure using selective atomic layer deposition | Toshiharu Furukawa, David V. Horak, Charles W. Koburger, III | 2006-08-01 |
| 7071047 | Method of forming buried isolation regions in semiconductor substrates and semiconductor devices with buried isolation regions | Toshiharu Furukawa, Mark C. Hakey, David V. Horak, Charles W. Koburger, III | 2006-07-04 |
| 7038299 | Selective synthesis of semiconducting carbon nanotubes | Toshiharu Furukawa, Mark C. Hakey, David V. Horak, Charles W. Koburger, III, Peter H. Mitchell +1 more | 2006-05-02 |
| 7030008 | Techniques for patterning features in semiconductor devices | Scott D. Allen, Katherina Babich, Arpan Mahorowala, Dirk Pfeiffer, Richard Wise | 2006-04-18 |
| 6998204 | Alternating phase mask built by additive film deposition | Toshiharu Furukawa, Mark C. Hakey, David V. Horak, Charles W. Koburger, III, Peter H. Mitchell +1 more | 2006-02-14 |
| 6998332 | Method of independent P and N gate length control of FET device made by sidewall image transfer technique | Toshiharu Furukawa, William H. Ma | 2006-02-14 |
| 6995065 | Selective post-doping of gate structures by means of selective oxide growth | Anthony I. Chou, Toshiharu Furukawa | 2006-02-07 |
| 6995051 | Irradiation assisted reactive ion etching | Toshiharu Furukawa, Mark C. Hakey, David V. Horak | 2006-02-07 |
| 6989323 | Method for forming narrow gate structures on sidewalls of a lithographically defined sacrificial material | Bruce B. Doris, Toshiharu Furukawa, Mark C. Hakey, David V. Horak, Charles W. Koburger, III | 2006-01-24 |
| 6989308 | Method of forming FinFET gates without long etches | Toshiharu Furukawa, Mark C. Hakey, David Vaclav Hofak, Charles W. Koburger, III, Peter H. Mitchell +1 more | 2006-01-24 |
| 6963132 | Integrated semiconductor device having co-planar device surfaces | Mark C. Hakey, David V. Horak, Harold G. Linde, Edmund J. Sprogis | 2005-11-08 |
| 6940134 | Semiconductor with contact contacting diffusion adjacent gate electrode | Toshiharu Furukawa, Mark C. Hakey, David V. Horak | 2005-09-06 |
| 6936879 | Increased capacitance trench capacitor | Toshiharu Furukawa, Mark C. Hakey, William H. Ma | 2005-08-30 |