Issued Patents All Time
Showing 151–175 of 220 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7065602 | Circuit and method for pipelined insertion | Robert S. Horton, David W. Milton, Clarence R. Ogilvie, Paul M. Schanely | 2006-06-20 |
| 7058914 | Automatic latch compression/reduction | Jack R. Smith | 2006-06-06 |
| 7053712 | Method and apparatus for controlling common-mode output voltage in fully differential amplifiers | Anthony R. Bonaccio, Hayden C. Cranford, Jr., Michael A. Sorna | 2006-05-30 |
| 7000214 | Method for designing an integrated circuit having multiple voltage domains | Joseph A. Iadanza, Raminderpal Singh, Ivan L. Wemple | 2006-02-14 |
| 6996795 | Data processing in digital systems | Kenneth J. Goodnow, Clarence R. Ogilvie | 2006-02-07 |
| 6985004 | Wiring optimizations for power | John M. Cohn, Alvar A. Dean, Amir Farrahi, David J. Hathaway, Thomas Lepsic +2 more | 2006-01-10 |
| 6978234 | Configurable real prototype hardware using cores and memory macros | Robert P. Battaline, Emory D. Keller | 2005-12-20 |
| 6964026 | Method of updating a semiconductor design | William P. Moore | 2005-11-08 |
| 6954085 | System and method for dynamically executing a function in a programmable logic array | Kenneth J. Goodnow, Clarence R. Ogilvie, Christopher B. Reynolds, Jack R. Smith | 2005-10-11 |
| 6954920 | Method, program product, and design tool for automatic transmission line selection in application specific integrated circuits | Peter Joel Jenkins, Raminderpal Singh | 2005-10-11 |
| 6944698 | Method and apparatus for providing bus arbitrations in a data processing system | W. Riyon Harding, Thomas Lepsic | 2005-09-13 |
| 6934656 | Auto-linking of function logic state with testcase regression list | Jason M. Norman, Nancy H. Pratt | 2005-08-23 |
| 6880074 | In-line code suppression | Patrick E. Perry | 2005-04-12 |
| 6834353 | Method and apparatus for reducing power consumption of a processing integrated circuit | Jack R. Smith | 2004-12-21 |
| 6825711 | Power reduction by stage in integrated circuit | John M. Cohn, Kenneth J. Goodnow, Scott Whitney Gould, Douglas W. Stout | 2004-11-30 |
| 6820254 | Method and system for optimizing code using an optimizing coprocessor | Jack R. Smith | 2004-11-16 |
| 6794706 | Applications of space-charge-limited conduction induced current increase in nitride-oxide dielectric capacitors: voltage regulator for power supply system and others | Fen Chen, Rajarao Jammy, Baozhen Li | 2004-09-21 |
| 6792582 | Concurrent logical and physical construction of voltage islands for mixed supply voltage designs | John M. Cohn, Alvar A. Dean, David J. Hathaway, David E. Lackey, Thomas Lepsic +2 more | 2004-09-14 |
| 6720673 | Voltage island fencing | Rafael Blanco | 2004-04-13 |
| 6711719 | Method and apparatus for reducing power consumption in VLSI circuit designs | John M. Cohn, Alvar A. Dean, Amir Farrahi, David J. Hathaway, Thomas Lepsic +2 more | 2004-03-23 |
| 6687883 | System and method for inserting leakage reduction control in logic circuits | John M. Cohn, Alvar A. Dean, David J. Hathaway | 2004-02-03 |
| 6678847 | Real time function view system and method | Patrick E. Perry | 2004-01-13 |
| 6658634 | Logic power optimization algorithm | Kenneth J. Goodnow, Michel S. Michail, Clarence R. Ogilvie, Wilbur D. Pricer | 2003-12-02 |
| 6636995 | Method of automatic latch insertion for testing application specific integrated circuits | Alvar A. Dean, Joseph A. Iadanza, David E. Lackey | 2003-10-21 |
| 6604174 | Performance based system and method for dynamic allocation of a unified multiport cache | Alvar A. Dean, Kenneth J. Goodnow, Stephen W. Mahin, Wilbur D. Pricer, Dana J. Thygesen | 2003-08-05 |