Issued Patents All Time
Showing 201–220 of 220 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6097243 | Device and method to reduce power consumption in integrated semiconductor devices using a low power groggy mode | Claude L. Bertin, William Robert Patrick Tonti, Alvar A. Dean, Wilbur D. Pricer, Patrick E. Perry +1 more | 2000-08-01 |
| 6081135 | Device and method to reduce power consumption in integrated semiconductor devices | Kenneth J. Goodnow, Michel S. Michail, Clarence R. Ogilvie, Wilbur D. Pricer | 2000-06-27 |
| 6054877 | Low power multiplexer circuit | — | 2000-04-25 |
| 6026471 | Anticipating cache memory loader and method | Kenneth J. Goodnow, Clarence R. Ogilvie, Wilbur D. Pricer | 2000-02-15 |
| 5986962 | Internal shadow latch | Claude L. Bertin, Kenneth J. Goodnow, Wilbur D. Pricer | 1999-11-16 |
| 5918246 | Apparatus and method for prefetching data based on information contained in a compiler generated program map | Kenneth J. Goodnow, Clarence R. Ogilvie, Wilbur D. Pricer | 1999-06-29 |
| 5902044 | Integrated hot spot detector for design, analysis, and control | Wilbur D. Pricer, Kenneth J. Goodnow, Michel S. Michail, Janak G. Patel | 1999-05-11 |
| 5874833 | True/complement output bus for reduced simulataneous switching noise | Patrick E. Perry | 1999-02-23 |
| 5867725 | Concurrent multitasking in a uniprocessor | Patrick Wai-Wah Fung | 1999-02-02 |
| 5835504 | Soft fuses using bist for cache self test | David K. Balkin, Robert M. Houle, Kenneth Torino | 1998-11-10 |
| 5832284 | Self regulating temperature/performance/voltage scheme for micros (X86) | Michel S. Michail, Wilbur D. Pricer | 1998-11-03 |
| 5781922 | Page boundary caches | George M. Braceras, Kenneth J. Goodnow | 1998-07-14 |
| 5761719 | On-chip memory map for processor cache macro | Stephen W. Mahin, Kevin W. McCullen, Daniel M. Wronski | 1998-06-02 |
| 5594895 | Method and apparatus for switching between clock generators only when activity on a bus can be stopped | Jon H. Raymond | 1997-01-14 |
| 5564042 | Asynchronous clock switching between first and second clocks by extending phase of current clock and switching after a predetermined time and appropriated transitions | Timothy J. Vonreyn | 1996-10-08 |
| 5459843 | RISC-type pipeline processor having N slower execution units operating in parallel interleaved and phase offset manner with a faster fetch unit and a faster decoder | Gordon Taylor Davis, John J. Reilly, Baiju D. Mandalia, Michael G. Holung, William R. Robinson, Jr. | 1995-10-17 |
| 5440689 | Interprocessor communication system for direct processor to processor communication between internal general purpose registers transparent to the execution of processors thereof | John J. Reilly | 1995-08-08 |
| 5357617 | Method and apparatus for substantially concurrent multiple instruction thread processing by a single pipeline processor | Gordon Taylor Davis | 1994-10-18 |
| 5300831 | Logic macro and protocol for reduced power consumption during idle state | Dac C. Pham, Jonathan H. Raymond | 1994-04-05 |
| 4833602 | Signal generator using modulo means | Jack Levy | 1989-05-23 |