Issued Patents All Time
Showing 26–45 of 45 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8942052 | Complementary metal-oxide-semiconductor (CMOS) min/max voltage circuit for switching between multiple voltages | William V. Huott, Michael Kugel, Juergen Pille, Dieter Wendel | 2015-01-27 |
| 8659963 | Enhanced power savings for memory arrays | Osama Dengler, Stefan Payer, Philipp Salz | 2014-02-25 |
| 8422313 | Reduced power consumption memory circuitry | Stefan Buettner, David A. Hrusecky, Werner Juchmes, Wolfgang Penth | 2013-04-16 |
| 8237481 | Low power programmable clock delay generator with integrated decode function | Yuen H. Chan, Michael Ju Hyeok Lee, Juergen Pille | 2012-08-07 |
| 8086657 | Adder structure with midcycle latch for power reduction | Wilhelm Haller, Christoph Wandel, Ulrich Weiss | 2011-12-27 |
| 7936198 | Progamable control clock circuit for arrays | Michael Ju Hyeok Lee, Yuen H. Chan, Juergen Pille | 2011-05-03 |
| 7936638 | Enhanced programmable pulsewidth modulating circuit for array clock generation | Yuen H. Chan, Michael Ju Hyeok Lee, Tobias Werner | 2011-05-03 |
| 7813163 | Single-ended read and differential write scheme | Juergen Pille, Otto Wagner, Sebastian Ehrenreich | 2010-10-12 |
| 7755394 | Circuit combining level shift function with gated reset | Thomas Froehnel, Guenter Mayer, Otto Wagner | 2010-07-13 |
| 7650535 | Array delete mechanisms for shipping a microprocessor with defective arrays | Norbert Hagspiel, William V. Huott, Frank Lehnert, Brian R. Prasky, Richard F. Rizzolo | 2010-01-19 |
| 7406495 | Adder structure with midcycle latch for power reduction | Wilhelm Haller, Christoph Wandel, Ulrich Weiss | 2008-07-29 |
| 7295481 | Power saving by disabling cyclic bitline precharge | Juergen Pille, Christian Schweizer, Klaus Thumm | 2007-11-13 |
| 7224190 | Midcycle latch for power saving and switching reduction | Wilhelm Haller, Monika Strohmer, Klaus Thumm | 2007-05-29 |
| 7095252 | Charge sharing reduction by applying intrinsic parallelism in complex dynamic domino type CMOS gates | Michael A. Haase, Wilhelm Haller, Christoph Wandel | 2006-08-22 |
| 6990038 | Clock driver and boundary latch for a multi-port SRAM | Yuen H. Chan, Timothy Charest, Rajiv V. Joshi | 2006-01-24 |
| 6918119 | Method and system to improve usage of an instruction window buffer in multi-processor, parallel processing environments | Wilhelm Haller, Jens Leenstra, Dieter Wendel, Friedrich-Christian Wernicke | 2005-07-12 |
| 6785781 | Read/write alignment scheme for port reduction of multi-port SRAM cells | Jens Leenstra, Juergen Pille, Dieter Wendel | 2004-08-31 |
| 6681313 | Method and system for fast access to a translation lookaside buffer | Son Dao Trong, Luis Parga Cacheiro, Hans-Werner Tast | 2004-01-20 |
| 6629215 | Multiple port memory apparatus | Juergen Pille, Dieter Wendel, George McNeil Lattimore | 2003-09-30 |
| 6496398 | Content addressable memory | Gerhard Hellner, Otto Wagner | 2002-12-17 |