Issued Patents All Time
Showing 101–110 of 110 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5757050 | Field effect transistor having contact layer of transistor gate electrode material | Eric Adler, Subhash B. Kulkarni, Werner Rausch, Luigi Ternullo, Jr. | 1998-05-26 |
| 5744384 | Semiconductor structures which incorporate thin film transistors | Eric Adler, Subhash B. Kulkarni, Werner Rausch, Luigi Ternullo, Jr. | 1998-04-28 |
| 5677563 | Gate stack structure of a field effect transistor | John Cronin, Carter W. Kaanta, Darrell Meulemans, Gordon Seth Starkey | 1997-10-14 |
| 5675185 | Semiconductor structure incorporating thin film transistors with undoped cap oxide layers | Bomy Chen, Subhash B. Kulkarni, Jerome B. Lasky, Edward J. Nowak, Werner Rausch +1 more | 1997-10-07 |
| 5672901 | Structure for interconnecting different polysilicon zones on semiconductor substrates for integrated circuits | John R. Abernathey, Paul C. Parries, Julie Anne Springer | 1997-09-30 |
| 5670812 | Field effect transistor having contact layer of transistor gate electrode material | Eric Adler, Subhash B. Kulkarni, Werner Rausch, Luigi Ternullo, Jr. | 1997-09-23 |
| 5510295 | Method for lowering the phase transformation temperature of a metal silicide | Cyril Cabral, Jr., Lawrence A. Clevenger, Francois M. d'Heurle, James M. E. Harper, Glen L. Miles +1 more | 1996-04-23 |
| 5496771 | Method of making overpass mask/insulator for local interconnects | John Cronin, Carter W. Kaanta, Darrell Meulemans, Gordon Seth Starkey | 1996-03-05 |
| 5485095 | Fabrication test circuit and method for signalling out-of-spec resistance in integrated circuit structure | John E. Bertsch, Edward J. Nowak, Minh H. Tong | 1996-01-16 |
| 5453400 | Method and structure for interconnecting different polysilicon zones on semiconductor substrates for integrated circuits | John R. Abernathey, Paul C. Parries, Julie Anne Springer | 1995-09-26 |